Commit b028f715 authored by wdenk's avatar wdenk
Browse files

* Patch by Yuli Barcohen, 3 Dec 2003:

  "revive" U-Boot support for old Motorola MPC860ADS board

* Patch by Cam(ilo?), 03 Dec 2003:
  make examples build even with broken Montavista objcopy

* Patch by Pavel Bartusek, 27 Nov 2003:
  fix conversion problem with "bootretry" evironment variable
parent b4676a25
......@@ -2,6 +2,15 @@
Changes since U-Boot 1.0.0:
======================================================================
* Patch by Yuli Barcohen, 3 Dec 2003:
"revive" U-Boot support for old Motorola MPC860ADS board
* Patch by Cam(ilo?), 03 Dec 2003:
make examples build even with broken Montavista objcopy
* Patch by Pavel Bartusek, 27 Nov 2003:
fix conversion problem with "bootretry" evironment variable
* Patch by Andre Schwarz, 24 Nov 2003:
add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
......
......@@ -115,6 +115,7 @@ SUBDIRS = tools \
examples \
post \
post/cpu
.PHONY : $(SUBDIRS)
#########################################################################
#########################################################################
......@@ -150,7 +151,7 @@ $(LIBS):
$(SUBDIRS):
@echo "#### MAKE $@ ####"
$(MAKE) -C $@
$(MAKE) -C $@ all
gdbtools:
$(MAKE) -C tools/gdb || exit 1
......
......@@ -22,9 +22,9 @@
#
#
# FADS boards
# Motorola old MPC821/860ADS, MPC8xxFADS, and new MPC866ADS boards
#
#TEXT_BASE = 0xFE000000
TEXT_BASE = 0x02800000
OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
TEXT_BASE = 0xFE000000
#TEXT_BASE = 0x02800000
#OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
......@@ -360,7 +360,11 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
switch (noMbytes) {
case 4: /* 4 Mbyte uses only CS2 */
#ifdef CONFIG_ADS
memctl->memc_mamr = 0xc0a21114;
#else
memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
#endif
memctl->memc_or2 = 0xffc00800; /* 4M */
break;
......@@ -393,17 +397,18 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
memctl->memc_br2 = 0x81 + base; /* use upma */
*((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
/* if no dimm is inserted, noMbytes is still detected as 8m, so
* sanity check top and bottom of memory */
*((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
/* check bytes / 2 because dram_size tests at base+bytes, which
* is not mapped */
if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
return -1;
}
if (noMbytes == 8)
if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
return -1;
}
return 0;
}
......
#include <config.h>
#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */
#include <common.h>
void
......@@ -40,3 +43,5 @@ fast_blink(unsigned int n)
signal_delay(0x00100000);
}
}
#endif /* !CONFIG_ADS */
......@@ -22,9 +22,6 @@
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
......@@ -33,41 +30,30 @@ SECTIONS
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/start.o (.text)
/*
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
. = env_offset;
common/environment.o(.text)
*/
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.fixup)
......@@ -136,11 +122,7 @@ SECTIONS
*(.bss)
*(COMMON)
}
. = ALIGN(256 * 1024);
.ppcenv :
{
common/environment.o (.ppcenv)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
......@@ -57,7 +57,7 @@
#include <command.h>
#include <config.h>
#include <pcmcia.h>
#if defined(CONFIG_IDE_8xx_PCCARD) && defined(CONFIG_8xx)
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#endif
#if defined(CONFIG_LWMON)
......
......@@ -505,7 +505,7 @@ void init_cmd_timeout(void)
char *s = getenv ("bootretry");
if (s != NULL)
retry_time = (int)simple_strtoul(s, NULL, 10);
retry_time = (int)simple_strtol(s, NULL, 10);
else
retry_time = CONFIG_BOOT_RETRY_TIME;
......
......@@ -145,9 +145,7 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_R360MPI) || \
defined(CONFIG_RPXCLASSIC) || \
defined(CONFIG_RPXLITE) || \
defined(CONFIG_SPD823TS) || \
defined(CONFIG_MPC86xADS) || \
(defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
defined(CONFIG_SPD823TS)
memctl->memc_br0 = CFG_BR0_PRELIM;
#endif
......
......@@ -153,7 +153,7 @@ int serial_init (void)
# endif
#endif
#if defined(CONFIG_FADS)
#if defined(CONFIG_FADS) || defined(CONFIG_ADS)
/* Enable RS232 */
#if defined(CONFIG_8xx_CONS_SMC1)
*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
......
......@@ -104,7 +104,7 @@ $(LIB): .depend $(LIBOBJS)
$(OBJCOPY) -O srec $(<:.o=) $@
%.bin: %.srec
$(OBJCOPY) -O binary $< $@ 2>/dev/null
$(OBJCOPY) -O binary $(<:.srec=) $@ 2>/dev/null
#########################################################################
......
......@@ -16,29 +16,31 @@
* High Level Configuration Options
* (easy to change)
*/
#include <mpc8xx_irq.h>
/* Board type */
#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */
/* Processor type */
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_ADS 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 19200 /* console baudrate */
#define CONFIG_PCMCIA 1 /* To enable PCMCIA support */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE 0x7F
#define CONFIG_BAUDRATE 38400 /* Console baudrate */
/* CFG_8XX_FACT * CFG_8XX_XIN = 50 MHz */
#if 0
#define CFG_8XX_XIN 32768 /* 32.768 kHz input frequency */
#define CFG_8XX_FACT 0x5F6 /* Multiply by 1526 */
/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */
#else
#define CFG_8XX_XIN 4000000 /* 4 MHz input frequency */
#define CFG_8XX_FACT 12 /* Multiply by 12 */
#endif
#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_DRAM_50MHZ 1
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
......@@ -47,11 +49,11 @@
#endif
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
#define CONFIG_BOOTCOMMAND \
"dhcp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
......@@ -60,18 +62,16 @@
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#if 0 /* private command defs */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_I2C | \
CFG_CMD_IDE | CFG_CMD_PCMCIA)
#endif
/* default command defs */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_PCMCIA \
| CFG_CMD_PING \
)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
......@@ -103,7 +103,7 @@
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xfff00000
#define CFG_IMMR 0xFF000000
#define CFG_IMMR_SIZE ((uint)(64 * 1024))
/*-----------------------------------------------------------------------
......@@ -121,13 +121,6 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
/*
* For booting Linux, the board info and command line data
......@@ -138,6 +131,9 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_BASE TEXT_BASE
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
......@@ -148,9 +144,14 @@
#undef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve one flash sector
(256 KB) for monitor */
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
/* the other CS:s are determined by looking at parameters in BCSRx */
......@@ -162,6 +163,15 @@
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* I2C configuration
*/
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE 0x7F
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
......@@ -176,7 +186,7 @@
#endif
/*-----------------------------------------------------------------------
* SUMCR - SIU Module Configuration 11-6
* SUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
......@@ -234,40 +244,22 @@
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
* BR0 and OR0 (FLASH)
* BR1 and OR1 (BCSR)
*/
/* the other CS:s are determined by looking at parameters in BCSRx */
#define BCSR_ADDR ((uint) 0xff010000)
#define BCSR_SIZE ((uint)(64 * 1024))
#define FLASH_BASE0_PRELIM 0xfe000000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
#define CFG_REMAP_OR_AM 0xff000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xffe00000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xff800000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#ifdef USE_REAL_FLASH_VALUES
/*
* These values fit our FADS860T ...
* The "default" behaviour with 1Mbyte initial doesn't work for us!
*/
#define CFG_BR0_PRELIM 0x0fe000001 /* Real values for the board */
#define CFG_OR0_PRELIM 0x0ffe00d34
#define CFG_BR2_PRELIM 0x000000081
#define CFG_OR2_PRELIM 0x0ff000800
#else
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
#endif
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V)
/* BCSRx - Board Control and Status Registers */
/* #define CFG_OR1_REMAP CFG_OR0_REMAP */
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
......@@ -275,9 +267,6 @@
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
......@@ -286,20 +275,6 @@
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#define CFG_MAMR 0x13a01114
/*
* Internal Definitions
*
......@@ -310,11 +285,10 @@
/* values according to the manual */
#define BCSR0 ((uint) (BCSR_ADDR + 00))
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
#define BCSR0 (BCSR_ADDR + 0x00)
#define BCSR1 (BCSR_ADDR + 0x04)
#define BCSR2 (BCSR_ADDR + 0x08)
#define BCSR3 (BCSR_ADDR + 0x0c)
/*-----------------------------------------------------------------------
......@@ -322,6 +296,10 @@
*-----------------------------------------------------------------------
*
*/
#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
......@@ -331,7 +309,6 @@
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff
*-----------------------------------------------------------------------
......@@ -346,7 +323,6 @@
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
/* #define CFG_ATA_BASE_ADDR 0xFE100000 */
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
#define CFG_ATA_IDE0_OFFSET 0x0000
......@@ -354,6 +330,8 @@
#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
#define CONFIG_DISK_SPINUP_TIME 1000000
#undef CONFIG_DISK_SPINUP_TIME /* usin Compact Flash */
/* (F)ADS bitvalues by Helmut Buchsbaum
* see MPC8xxADS User's Manual for a proper description
......@@ -399,65 +377,6 @@
#define BCSR3_BREVN1 ((ushort)0x0008)
#define BCSR3_BREVN2_MASK ((ushort)0x0003)
#define BCSR4_ETHLOOP ((uint)0x80000000)
#define BCSR4_TFPLDL ((uint)0x40000000)
#define BCSR4_TPSQEL ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0 ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1 ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE ((uint)0x00080000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE ((uint)0x00080000)
#endif /* CONFIG_MPC850 */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
#ifdef CONFIG_MPC860T
/* Interrupt level assignments.
*/
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
#endif /* CONFIG_MPC860T */
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
......@@ -466,17 +385,4 @@
*/
#define _MACH_8xx (_MACH_ads)
#if 0
#define CONFIG_DISK_SPINUP_TIME 1000000
#endif
#undef CONFIG_DISK_SPINUP_TIME /* usin Compact Flash */
/* PCMCIA configuration
*/
#define PCMCIA_MAX_SLOTS 2
#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif
#endif /* _CONFIG_ADS860_H */
......@@ -30,7 +30,6 @@
* High Level Configuration Options
* (easy to change)
*/
#include <mpc8xx_irq.h>
/* board type */
#define CONFIG_FADS 1 /* old/new FADS + new ADS */
......@@ -58,9 +57,6 @@
/* in general, we always know this for FADS+new ADS anyway */
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
/* most vanilla kernels do not like this, set to 0 if in doubt */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#if 1
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
......@@ -163,11 +159,11 @@
# define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */
#endif
#define CFG_FLASH_BASE 0x02800000
#define CFG_FLASH_BASE TEXT_BASE
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
......@@ -184,7 +180,7 @@
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000
......@@ -276,14 +272,11 @@
#define BCSR_ADDR ((uint) 0xFF010000)
#define BCSR_SIZE ((uint)(64 * 1024))
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#ifdef USE_REAL_FLASH_VALUES
/*
* These values fit our FADS860T ...
......@@ -297,7 +290,6 @@
#endif
/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_REMAP CFG_OR0_REMAP
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
......@@ -316,7 +308,7 @@
#define PCMCIA_MEM_ADDR ((uint)0xff020000)
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))