Commit b1881575 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-arm

parents 683e9f1e 2ea88b06
......@@ -572,6 +572,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Andreas Biemann <andreas.devel@gmail.com>
at91rm9200ek at91rm9200
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
......@@ -808,6 +812,15 @@ Greg Ungerer <greg.ungerer@opengear.com>
cm4116 ks8695p
cm4148 ks8695p
Marek Vasut <marek.vasut@gmail.com>
balloon3 xscale
colibri_pxa270 xscale
palmld xscale
palmtc xscale
vpac270 xscale
zipitz2 xscale
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
SFFSDR ARM926EJS
......
......@@ -468,12 +468,7 @@ LIST_at91=" \
## Xscale Systems
#########################################################################
LIST_pxa="$(boards_by_cpu pxa)
polaris \
trizepsiv \
vpac270_nor \
vpac270_onenand \
"
LIST_pxa="$(boards_by_cpu pxa)"
LIST_ixp="$(boards_by_cpu ixp)
pdnb3 \
......
......@@ -358,7 +358,7 @@ $(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(TEXT_BASE) -d $< $@
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
......@@ -1027,23 +1027,6 @@ scpu_config: unconfig
fi
@$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
polaris_config \
trizepsiv_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring polaris,$@)" ] ; then \
echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
vpac270_nor_config \
vpac270_onenand_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring onenand,$@)" ] ; then \
echo "#define CONFIG_ONENAND_U_BOOT" \
>>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
#########################################################################
## ARM1136 Systems
#########################################################################
......
......@@ -2275,6 +2275,19 @@ Configuration Settings:
all data for the Linux kernel must be between "bootm_low"
and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
- CONFIG_SYS_BOOT_RAMDISK_HIGH:
Enable initrd_high functionality. If defined then the
initrd_high feature is enabled and the bootm ramdisk subcommand
is enabled.
- CONFIG_SYS_BOOT_GET_CMDLINE:
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
- CONFIG_SYS_BOOT_GET_KBD:
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
- CONFIG_SYS_MAX_FLASH_BANKS:
Max number of Flash memory banks
......
......@@ -33,11 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
# needed for relocation
PLATFORM_RELFLAGS += -fPIC
endif
ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
endif
......@@ -72,3 +67,10 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
endif
endif
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
# needed for relocation
ifndef CONFIG_NAND_SPL
PLATFORM_LDFLAGS += -pie
endif
endif
......@@ -89,48 +89,35 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word _end
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarel_start_ofs
_datarel_start_ofs:
.word __datarel_start - _start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _datarelrolocal_start_ofs
_datarelrolocal_start_ofs:
.word __datarelrolocal_start - _start
.globl _got_start
_got_start:
.word __got_start
.globl _datarellocal_start_ofs
_datarellocal_start_ofs:
.word __datarellocal_start - _start
.globl _got_end
_got_end:
.word __got_end
#endif
.globl _datarelro_start_ofs
_datarelro_start_ofs:
.word __datarelro_start - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
......@@ -225,9 +212,8 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
......@@ -239,36 +225,54 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
ble fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
......@@ -283,24 +287,34 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
ldr pc, _nand_boot
_nand_boot: .word nand_boot
ldr r0, _nand_boot_ofs
adr r1, _start
add pc, r0, r1
_nand_boot_ofs
: .word nand_boot - _start
#else
jump_2_ram:
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
_board_init_r_ofs:
.word board_init_r - _start
#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
......@@ -375,8 +389,11 @@ stack_setup:
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
adr r2, _start
ldr r0, _bss_start_ofs /* find start of bss segment */
add r0, r0, r2
ldr r1, _bss_end_ofs /* stop here */
add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
......@@ -386,15 +403,19 @@ clbss_l:str r2, [r0] /* clear loop... */
bne clbss_l
#endif
ldr pc, _start_armboot
ldr r0, _start_armboot_ofs
adr r1, _start
add r0, r0, r1
ldr pc, r0
_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
_start_armboot: .word nand_boot
.word nand_boot - _start
#else
#ifdef CONFIG_ONENAND_IPL
_start_armboot: .word start_oneboot
.word start_oneboot - _start
#else
_start_armboot: .word start_armboot
.word start_armboot - _start
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_NAND_SPL */
......@@ -487,7 +508,7 @@ cpu_init_crit:
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
#else
ldr r2, _armboot_start
adr r2, _start
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#endif
......@@ -524,8 +545,8 @@ cpu_init_crit:
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
#else
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
adr r13, _start @ setup our mode stack (enter in banked mode)
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
#endif
......
......@@ -59,11 +59,14 @@ SECTIONS
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
......@@ -73,4 +76,10 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
......@@ -11,47 +11,46 @@
* (at your option) any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
static unsigned long cpu_clk_rate_hz;
static unsigned long main_clk_rate_hz;
static unsigned long mck_rate_hz;
static unsigned long plla_rate_hz;
static unsigned long pllb_rate_hz;
static u32 at91_pllb_usb_init;
#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
DECLARE_GLOBAL_DATA_PTR;
unsigned long get_cpu_clk_rate(void)
{
return cpu_clk_rate_hz;
return gd->cpu_clk_rate_hz;
}
unsigned long get_main_clk_rate(void)
{
return main_clk_rate_hz;
return gd->main_clk_rate_hz;
}
unsigned long get_mck_clk_rate(void)
{
return mck_rate_hz;
return gd->mck_rate_hz;
}
unsigned long get_plla_clk_rate(void)
{
return plla_rate_hz;
return gd->plla_rate_hz;
}
unsigned long get_pllb_clk_rate(void)
{
return pllb_rate_hz;
return gd->pllb_rate_hz;
}
u32 get_pllb_init(void)
{
return at91_pllb_usb_init;
return gd->at91_pllb_usb_init;
}
static unsigned long at91_css_to_rate(unsigned long css)
......@@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return main_clk_rate_hz;
return gd->main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
return plla_rate_hz;
return gd->plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
return pllb_rate_hz;
return gd->pllb_rate_hz;
}
return 0;
......@@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
main_clk_rate_hz = main_clock;
gd->main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
......@@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
#endif
/*
......@@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = mck_rate_hz;
gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
/* mdiv */
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
cpu_clk_rate_hz = freq;
gd->cpu_clk_rate_hz = freq;
return 0;
}
......@@ -30,55 +30,63 @@
#include <asm/arch/io.h>
#include <div64.h>
#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
* (See the relevant data sheets to understand that this really works)
*
* We do also mimic the typical powerpc way of incrementing
* two 32 bit registers called tbl and tbu.
*
* Those registers increment at 1/16 the main clock rate.
*/
#define TIMER_LOAD_VAL 0xfffff
static ulong timestamp;
static ulong lastinc;
static ulong timer_freq;
#define TIMER_LOAD_VAL 0xfffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, timer_freq);
do_div(tick, gd->timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= timer_freq;
usec *= gd->timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
/* nothing really to do with interrupts, just starts up a counter. */
/*
* Use the PITC in full 32 bit incrementing mode
*/
int timer_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
/* Enable PITC Clock */
writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
reset_timer_masked();
timer_freq = get_mck_clk_rate() >> 4;
gd->timer_rate_hz = gd->mck_rate_hz / 16;
gd->tbu = gd->tbl = 0;
return 0;
}
/*
* timer without interrupts
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)