Commit b21b2081 authored by Bin Meng's avatar Bin Meng Committed by Simon Glass
Browse files

x86: crownbay: Add pci devices in the dts file



The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
parent 1eb47efc
......@@ -32,6 +32,14 @@
};
chosen {
/*
* By default the legacy superio serial port is used as the
* U-Boot serial console. If we want to use UART from Topcliff
* PCH as the console, change this property to &pciuart#.
*
* For example, stdout-path = &pciuart0 will use the first
* UART on Topcliff PCH.
*/
stdout-path = "/serial";
};
......@@ -52,4 +60,77 @@
};
};
pci {
#address-cells = <3>;
#size-cells = <2>;
compatible = "intel,pci";
device_type = "pci";
pcie@17,0 {
#address-cells = <3>;
#size-cells = <2>;
compatible = "intel,pci";
device_type = "pci";
topcliff@0,0 {
#address-cells = <3>;
#size-cells = <2>;
compatible = "intel,pci";
device_type = "pci";
pciuart0: uart@a,1 {
compatible = "pci8086,8811.00",
"pci8086,8811",
"pciclass,070002",
"pciclass,0700",
"x86-uart";
reg = <0x00025100 0x0 0x0 0x0 0x0
0x01025110 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
clock-frequency = <1843200>;
current-speed = <115200>;
};
pciuart1: uart@a,2 {
compatible = "pci8086,8812.00",
"pci8086,8812",
"pciclass,070002",
"pciclass,0700",
"x86-uart";
reg = <0x00025200 0x0 0x0 0x0 0x0
0x01025210 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
clock-frequency = <1843200>;
current-speed = <115200>;
};
pciuart2: uart@a,3 {
compatible = "pci8086,8813.00",
"pci8086,8813",
"pciclass,070002",
"pciclass,0700",
"x86-uart";
reg = <0x00025300 0x0 0x0 0x0 0x0
0x01025310 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
clock-frequency = <1843200>;
current-speed = <115200>;
};
pciuart3: uart@a,4 {
compatible = "pci8086,8814.00",
"pci8086,8814",
"pciclass,070002",
"pciclass,0700",
"x86-uart";
reg = <0x00025400 0x0 0x0 0x0 0x0
0x01025410 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
clock-frequency = <1843200>;
current-speed = <115200>;
};
};
};
};
};
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