Commit b2871037 authored by Tom Warren's avatar Tom Warren Committed by Tom Warren

Tegra30: Add common CPU (shared) files

These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
Reviewed-by: default avatarStephen Warren <swarren@nvidia.com>
parent 5576aab5
......@@ -20,10 +20,14 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra AP (Application Processor) code */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clock.h>
#include <asm/arch-tegra/fuse.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
......@@ -58,6 +62,12 @@ int tegra_get_chip_type(void)
return TEGRA_SOC_T25;
}
break;
case CHIPID_TEGRA30:
switch (tegra_sku_id) {
case SKU_ID_T30:
return TEGRA_SOC_T30;
}
break;
}
/* unknown sku id */
return TEGRA_SOC_UNKNOWN;
......@@ -93,7 +103,7 @@ static u32 get_odmdata(void)
u32 bct_start, odmdata;
bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
......@@ -127,5 +137,5 @@ void s_init(void)
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
/* FIXME: should have ap20's L2 disabled too? */
/* FIXME: should have SoC's L2 disabled too? */
}
......@@ -54,16 +54,37 @@ unsigned int query_sdram_size(void)
reg = readl(&pmc->pmc_scratch20);
debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
/* bits 31:28 in OdmData are used for RAM size */
#if defined(CONFIG_TEGRA20)
/* bits 30:28 in OdmData are used for RAM size on T20 */
reg &= 0x70000000;
switch ((reg) >> 28) {
case 1:
return 0x10000000; /* 256 MB */
case 0:
case 2:
default:
return 0x20000000; /* 512 MB */
case 3:
return 0x40000000; /* 1GB */
}
#else /* Tegra30 */
/* bits 31:28 in OdmData are used for RAM size on T30 */
switch ((reg) >> 28) {
case 0:
case 1:
default:
return 0x10000000; /* 256 MB */
case 2:
return 0x20000000; /* 512 MB */
case 3:
return 0x30000000; /* 768 MB */
case 4:
return 0x40000000; /* 1GB */
case 8:
return 0x7ff00000; /* 2GB - 1MB */
}
#endif
}
int dram_init(void)
......@@ -82,19 +103,27 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
#if defined(CONFIG_TEGRA20)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
#elif defined(CONFIG_TEGRA_UARTA_GPU)
#elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
#else
#else
FUNCMUX_UART1_IRRX_IRTX,
#endif
#endif
FUNCMUX_UART2_IRDA,
-1,
FUNCMUX_UART4_GMC,
-1,
#else /* Tegra30 */
FUNCMUX_UART1_ULPI, /* UARTA */
-1,
-1,
-1,
-1,
#endif
};
/**
......
......@@ -22,12 +22,26 @@
*/
#include <common.h>
#include <linux/ctype.h>
#ifdef CONFIG_DISPLAY_CPUINFO
void upstring(char *s)
{
while (*s) {
*s = toupper(*s);
s++;
}
}
/* Print CPU information */
int print_cpuinfo(void)
{
puts("TEGRA20\n");
char soc_name[10];
strncpy(soc_name, CONFIG_SYS_SOC, 10);
upstring(soc_name);
puts(soc_name);
puts("\n");
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
......
......@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
* This is the place in SRAM where the SDRAM parameters are stored. There
* are 4 blocks, one for each RAM code
*/
#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188)
#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
/* TODO: If we later add support for the Misc GP controller, refactor this */
union xm2cfga_reg {
......
#
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
include $(TOPDIR)/config.mk
# The AVP is ARMv4T architecture so we must use special compiler
# flags for any startup files it might use.
LIB = $(obj)lib$(SOC)-common.o
COBJS-y += clock.o funcmux.o pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
This diff is collapsed.
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Tegra30 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config)
{
int bad_config = config != FUNCMUX_DEFAULT;
switch (id) {
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_ULPI:
pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_ULPI_DATA0);
pinmux_tristate_disable(PINGRP_ULPI_DATA1);
pinmux_tristate_disable(PINGRP_ULPI_DATA2);
pinmux_tristate_disable(PINGRP_ULPI_DATA3);
break;
}
break;
/* Add other periph IDs here as needed */
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
}
if (bad_config) {
debug("%s: invalid config %d for periph_id %d", __func__,
config, id);
return -1;
}
return 0;
}
This diff is collapsed.
......@@ -23,67 +23,27 @@
#include <asm/types.h>
/* Stabilization delays, in usec */
#define PLL_STABILIZATION_DELAY (300)
#define PLL_STABILIZATION_DELAY (300)
#define IO_STABILIZATION_DELAY (1000)
#define NVBL_PLLP_KHZ (216000)
#define PLLX_ENABLED (1 << 30)
#define CCLK_BURST_POLICY 0x20008888
#define SUPER_CCLK_DIVIDER 0x80000000
/* Calculate clock fractional divider value from ref and target frequencies */
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
/* Calculate clock frequency value from reference and clock divider value */
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
/* AVP/CPU ID */
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
#define PG_UP_TAG_0 0x0
#define CORESIGHT_UNLOCK 0xC5ACCE55;
/* AP20-Specific Base Addresses */
/* AP20 Base physical address of SDRAM. */
#define AP20_BASE_PA_SDRAM 0x00000000
/* AP20 Base physical address of internal SRAM. */
#define AP20_BASE_PA_SRAM 0x40000000
/* AP20 Size of internal SRAM (256KB). */
#define AP20_BASE_PA_SRAM_SIZE 0x00040000
/* AP20 Base physical address of flash. */
#define AP20_BASE_PA_NOR_FLASH 0xD0000000
/* AP20 Base physical address of boot information table. */
#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
/*
* Super-temporary stacks for EXTREMELY early startup. The values chosen for
* these addresses must be valid on ALL SOCs because this value is used before
* we are able to differentiate between the SOC types.
*
* NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
* stack is placed below the AVP stack. Once the CPU stack has been moved,
* the AVP is free to use the IRAM the CPU stack previously occupied if
* it should need to do so.
*
* NOTE: In multi-processor CPU complex configurations, each processor will have
* its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
* limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
* stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
* CPU.
*/
/* Common AVP early boot stack limit */
#define AVP_EARLY_BOOT_STACK_LIMIT \
(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
/* Common AVP early boot stack size */
#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
/* Common CPU early boot stack limit */
#define CPU_EARLY_BOOT_STACK_LIMIT \
(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
/* Common CPU early boot stack size */
#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM 0x40000000
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
......
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