Commit b38a5699 authored by Daniel Schwierzeck's avatar Daniel Schwierzeck Committed by Shinya Kuribayashi
Browse files

MIPS: Purple: Remove Purple support



The Purple SoC and eval board are not actively maintained since years.
This patch removes the support completely as aggreed with Wolfgang Denk.
Signed-off-by: default avatarDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: default avatarShinya Kuribayashi <skuribay@pobox.com>
parent 67a490d6
......@@ -919,7 +919,6 @@ Daniel Engstr
Wolfgang Denk <wd@denx.de>
incaip MIPS32 4Kc
purple MIPS64 5Kc
Thomas Lange <thomas@corelatus.se>
dbau1x00 MIPS32 Au1000
......
......@@ -507,9 +507,7 @@ LIST_mips4kc=" \
vct_premium_onenand_small \
"
LIST_mips5kc=" \
purple \
"
LIST_mips5kc=""
LIST_au1xx0=" \
dbau1000 \
......
......@@ -31,7 +31,6 @@ COBJS-y = cpu.o interrupts.o
SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o
COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o
COBJS-$(CONFIG_PURPLE) += asc_serial.o
COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
......
......@@ -3,47 +3,10 @@
*/
#include <config.h>
#ifdef CONFIG_PURPLE
#define serial_init asc_serial_init
#define serial_putc asc_serial_putc
#define serial_puts asc_serial_puts
#define serial_getc asc_serial_getc
#define serial_tstc asc_serial_tstc
#define serial_setbrg asc_serial_setbrg
#endif
#include <common.h>
#include <asm/inca-ip.h>
#include "asc_serial.h"
#ifdef CONFIG_PURPLE
#undef ASC_FIFO_PRESENT
#define TOUT_LOOP 100000
/* Set base address for second FPI interrupt control register bank */
#define SFPI_INTCON_BASEADDR 0xBF0F0000
/* Register offset from base address */
#define FBS_ISR 0x00000000 /* Interrupt status register */
#define FBS_IMR 0x00000008 /* Interrupt mask register */
#define FBS_IDIS 0x00000010 /* Interrupt disable register */
/* Interrupt status register bits */
#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */
#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */
#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */
#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */
#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */
#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */
#else
#define ASC_FIFO_PRESENT
#endif
#define SET_BIT(reg, mask) reg |= (mask)
#define CLEAR_BIT(reg, mask) reg &= (~mask)
......@@ -71,10 +34,8 @@ static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
int serial_init (void)
{
#ifdef CONFIG_INCA_IP
/* we have to set PMU.EN13 bit to enable an ASC device*/
INCAASC_PMU_ENABLE(13);
#endif
/* and we have to set CLC register*/
CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
......@@ -86,7 +47,6 @@ int serial_init (void)
/* select input port */
pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
#ifdef ASC_FIFO_PRESENT
/* TXFIFO's filling level */
SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
......@@ -98,25 +58,20 @@ int serial_init (void)
ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
#endif
/* enable error signals */
SET_BIT(pAsc->asc_con, ASCCON_FEN);
SET_BIT(pAsc->asc_con, ASCCON_OEN);
#ifdef CONFIG_INCA_IP
/* acknowledge ASC interrupts */
ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
/* disable ASC interrupts */
ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
#endif
#ifdef ASC_FIFO_PRESENT
/* set FIFOs into the transparent mode */
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
#endif
/* set baud rate */
serial_setbrg();
......@@ -132,11 +87,7 @@ void serial_setbrg (void)
ulong uiReloadValue, fdv;
ulong f_ASC;
#ifdef CONFIG_INCA_IP
f_ASC = incaip_get_fpiclk();
#else
f_ASC = ASC_CLOCK_RATE;
#endif
#ifndef INCAASC_USE_FDV
fdv = 2;
......@@ -261,15 +212,10 @@ static int serial_setopt (void)
void serial_putc (const char c)
{
#ifdef ASC_FIFO_PRESENT
uint txFl = 0;
#else
uint timeout = 0;
#endif
if (c == '\n') serial_putc ('\r');
#ifdef ASC_FIFO_PRESENT
/* check do we have a free space in the TX FIFO */
/* get current filling level */
do
......@@ -277,25 +223,9 @@ void serial_putc (const char c)
txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
}
while ( txFl == INCAASC_TXFIFO_FULL );
#else
while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
FBS_ISR_AB))
{
if (timeout++ > TOUT_LOOP)
{
break;
}
}
#endif
pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
#ifndef ASC_FIFO_PRESENT
*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
FBS_ISR_AT;
#endif
/* check for errors */
if ( pAsc->asc_con & ASCCON_OE )
{
......@@ -324,10 +254,6 @@ int serial_getc (void)
c = (char)(pAsc->asc_rbuf & symbol_mask);
#ifndef ASC_FIFO_PRESENT
*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
#endif
return c;
}
......@@ -335,19 +261,10 @@ int serial_tstc (void)
{
int res = 1;
#ifdef ASC_FIFO_PRESENT
if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
{
res = 0;
}
#else
if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
FBS_ISR_AR))
{
res = 0;
}
#endif
else if ( pAsc->asc_con & ASCCON_FE )
{
SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
......
......@@ -311,11 +311,7 @@ LEAF(dcache_enable)
* RETURNS: N/A
*
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
......
......@@ -67,9 +67,6 @@ _start:
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
......@@ -203,30 +200,6 @@ _start:
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
......@@ -337,17 +310,12 @@ relocate_code:
move a0, t1 /* a0 <-- destination addr */
sub a1, t2, t0 /* a1 <-- size */
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
......
......@@ -894,12 +894,7 @@
/* Module : EBU register address and bits */
/***********************************************************************/
#if defined(CONFIG_INCA_IP)
#define INCA_IP_EBU (0xB8000200)
#elif defined(CONFIG_PURPLE)
#define INCA_IP_EBU (0xB800D800)
#endif
/***********************************************************************/
......@@ -1495,12 +1490,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not
/* Module : ASC register address and bits */
/***********************************************************************/
#if defined(CONFIG_INCA_IP)
#define INCA_IP_ASC (0xB8000400)
#elif defined(CONFIG_PURPLE)
#define INCA_IP_ASC (0xBE500000)
#endif
/***********************************************************************/
......
......@@ -162,9 +162,6 @@ void board_init_f(ulong bootflag)
init_fnc_t **init_fnc_ptr;
ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_SYS_MONITOR_BASE;
ulong *s;
#ifdef CONFIG_PURPLE
void copy_code (ulong);
#endif
/* Pointer is writable since we allocated a register for it.
*/
......@@ -253,13 +250,6 @@ void board_init_f(ulong bootflag)
memcpy (id, (void *)gd, sizeof (gd_t));
/* On the purple board we copy the code in a special way
* in order to solve flash problems
*/
#ifdef CONFIG_PURPLE
copy_code(addr);
#endif
relocate_code (addr_sp, id, addr);
/* NOTREACHED - relocate_code() does not return */
......
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o sconsole.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Purple board with MIPS 5Kc CPU core
#
# ROM version
CONFIG_SYS_TEXT_BASE = 0xB0000000
# RAM version
#CONFIG_SYS_TEXT_BASE = 0x80100000
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/inca-ip.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
typedef unsigned long FLASH_PORT_WIDTH;
typedef volatile unsigned long FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFFFFFFFF
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define ORMASK(size) ((-size) & OR_AM_MSK)
#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg))
/* FLASH29 command register addresses */
#define FLASH29_REG_FIRST_CYCLE FLASH29_REG_ADRS (0x1555)
#define FLASH29_REG_SECOND_CYCLE FLASH29_REG_ADRS (0x2aaa)
#define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555)
#define FLASH29_REG_FOURTH_CYCLE FLASH29_REG_ADRS (0x4555)
#define FLASH29_REG_FIFTH_CYCLE FLASH29_REG_ADRS (0x5aaa)
#define FLASH29_REG_SIXTH_CYCLE FLASH29_REG_ADRS (0x6555)
/* FLASH29 command definitions */
#define FLASH29_CMD_FIRST 0xaaaaaaaa
#define FLASH29_CMD_SECOND 0x55555555
#define FLASH29_CMD_FOURTH 0xaaaaaaaa
#define FLASH29_CMD_FIFTH 0x55555555
#define FLASH29_CMD_SIXTH 0x10101010
#define FLASH29_CMD_SECTOR 0x30303030
#define FLASH29_CMD_PROGRAM 0xa0a0a0a0
#define FLASH29_CMD_CHIP_ERASE 0x80808080
#define FLASH29_CMD_READ_RESET 0xf0f0f0f0
#define FLASH29_CMD_AUTOSELECT 0x90909090
#define FLASH29_CMD_READ 0x70707070
#define IN_RAM_CMD_READ 0x1
#define IN_RAM_CMD_WRITE 0x2
#define FLASH_WRITE_CMD ((ulong)(flash_write_cmd) & 0x7)+0xbf008000
#define FLASH_READ_CMD ((ulong)(flash_read_cmd) & 0x7)+0xbf008000
typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs);
typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen);
typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value);
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static int write_word(flash_info_t *info, FPWV *dest, FPW data);
static void flash_get_offsets(ulong base, flash_info_t *info);
static flash_info_t *flash_get_info(ulong base);
static void load_cmd(ulong cmd);
static ulong in_ram_cmd = 0;
/******************************************************************************
*
* Don't change the program architecture
* This architecture assure the program
* can be relocated to scratch ram
*/
static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
{
int i,j;
FPW temp,temp1;
FPWV *str;
str = (FPWV *)string;
j= strLen/4;
if(cmd == FLASH29_CMD_AUTOSELECT)
{
*(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT;
}
if(cmd == FLASH29_CMD_READ)
{
i = 0;
while(i<j)
{
temp = *pFA++;
temp1 = *(int *)0xa0000000;
*(int *)0xbf0081f8 = temp1 + temp;
*str++ = temp;
i++;
}
}
if(cmd == FLASH29_CMD_READ_RESET)
{
*(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
}
*(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
}
/******************************************************************************
*
* Don't change the program architecture
* This architecture assure the program
* can be relocated to scratch ram
*/
static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
{
*(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
if (cmd == FLASH29_CMD_SECTOR)
{
*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
*(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
*(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
*pFA = FLASH29_CMD_SECTOR;
}
if (cmd == FLASH29_CMD_SIXTH)
{
*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
*(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
*(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
*(FLASH29_REG_SIXTH_CYCLE) = FLASH29_CMD_SIXTH;
}
if (cmd == FLASH29_CMD_PROGRAM)
{
*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_PROGRAM;
*pFA = value;
}
if (cmd == FLASH29_CMD_READ_RESET)
{
*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
}
*(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
}
static void load_cmd(ulong cmd)
{
ulong *src;
ulong *dst;
FUNCPTR_CP absEntry;
ulong func;
if (in_ram_cmd & cmd) return;
if (cmd == IN_RAM_CMD_READ)
{
func = (ulong)flash_read_cmd;
}
else
{
func = (ulong)flash_write_cmd;
}
src = (ulong *)(func & 0xfffffff8);
dst = (ulong *)0xbf008000;
absEntry = (FUNCPTR_CP)(0xbf0081d0);
absEntry(src,dst,0x38);
in_ram_cmd = cmd;
}
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
unsigned long size = 0;
int i;
load_cmd(IN_RAM_CMD_READ);
/* Init: no FLASHes known */
for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
ulong flashbase = PHYS_FLASH_1;
ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
/* Disable write protection */
*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
#if 1
memset(&flash_info[i], 0, sizeof(flash_info_t));
#endif
flash_info[i].size =
flash_get_size((FPW *)flashbase, &flash_info[i]);
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
i, flash_info[i].size);
}