Merge with /home/wd/git/u-boot/jon_loeliger

b4f15fda · Wolfgang Denk · b20d0032 · 07a2505f · b4f15fda · b4f15fda
Commit b4f15fda authored Aug 05, 2005 by Wolfgang Denk
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,51 @@
 Changes for U-Boot 1.1.3:
 ======================================================================

+* Patch by Jon Loeliger
+  Fix style issues primarily in 85xx and 83xx boards.
+    - C++ comments
+    - Trailing white space
+    - Indentation not by TAB
+    - Excessive amount of empty lines
+    - Trailing empty lines
+
+* Patch by Ron Alder, 11 Jul 2005
+    Add Xianghua Xiao and Lunsheng Wang's support for the
+    GDA MPC8540 EVAL board.
+
+* Patch by Eran Liberty
+  Add support for the Freescale MPC8349ADS board.
+
+* Patch by Jon Loeliger, 25 Jul 2005
+  Move the TSEC driver out of cpu/mpc85xx as it will be shared
+  by the upcoming mpc83xx family as well.
+
+* Patch by Jon Loeliger, 05 May 2005
+  Implemented support for MPC8548CDS board.
+  Added DDR II support based on SPD values for MPC85xx boards.
+  This roll-up patch also includes bugfies for the previously
+  published patches:
+    DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
+
+* Patch by Jon Loeliger, 10 Feb 2005
+  Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
+
+* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
+  For MPC85xxCDS:
+    Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
+    for faster flash parts.
+    Add documentation for BR/OR for FLASH.
+
+* Patch by Jon Loeliger 08 Feb 2005
+  Determine L2 Cache size dynamically on 85XX boards.
+
+* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
+  - Convert the CPM2 based functionality to use new CONFIG_CPM2
+    option rather than a myriad of CONFIG_MPC8560-like variants.
+    Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
+    Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
+    new CONFIG_CPM2 option to each 8260 board.
+
 * Add support for MicroSys PM856 board
  Patch by Josef Wagner, 03 Aug 2005


--- a/MAKEALL
+++ b/MAKEALL
@@ -107,14 +107,23 @@ LIST_8260="	\
 	ZPC1900								\
 "

+#########################################################################
+## MPC83xx Systems (includes 8349, etc.)
+#########################################################################
+
+LIST_83xx="	\
+	MPC8349ADS	\
+"
+
+
 #########################################################################
 ## MPC85xx Systems (includes 8540, 8560 etc.)
 #########################################################################

 LIST_85xx="	\
-	MPC8540ADS	MPC8541CDS	MPC8555CDS	MPC8560ADS	\
-	PM854		PM856		sbc8540		sbc8560		\
-	stxgp3		TQM8540						\
+	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8548CDS	\
+	MPC8555CDS	MPC8560ADS	PM854		PM856		\
+	sbc8540		sbc8560		stxgp3		TQM8540		\
 "

 #########################################################################
@@ -133,6 +142,7 @@ LIST_7xx="	\
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
 	  ${LIST_8xx}				\
 	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+	  ${LIST_83xx}				\
 	  ${LIST_85xx}				\
 	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"
@@ -250,7 +260,7 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
+	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
 	arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
 	microblaze| \
 	mips| \

--- a/Makefile
+++ b/Makefile
@@ -54,7 +54,7 @@ ifeq ($(HOSTARCH),ppc)
 CROSS_COMPILE =
 else
 ifeq ($(ARCH),ppc)
-CROSS_COMPILE = ppc_8xx-
+CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
 CROSS_COMPILE = arm-linux-
@@ -97,6 +97,9 @@ endif
 ifeq ($(CPU),ppc4xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
+ifeq ($(CPU),mpc83xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif
 ifeq ($(CPU),mpc85xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
@@ -1192,6 +1195,13 @@ M5282EVB_config :		unconfig
 TASREG_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd

+#########################################################################
+## MPC83xx Systems
+#########################################################################
+
+MPC8349ADS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
+
 #########################################################################
 ## MPC85xx Systems
 #########################################################################
@@ -1199,12 +1209,35 @@ TASREG_config :		unconfig
 MPC8540ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads

+MPC8540EVAL_config \
+MPC8540EVAL_33_config \
+MPC8540EVAL_66_config \
+MPC8540EVAL_33_slave_config \
+MPC8540EVAL_66_slave_config:      unconfig
+	@echo "" >include/config.h ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		echo -n "... 33 MHz PCI" ; \
+	else \
+		echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \
+		echo -n "... 66 MHz PCI" ; \
+	fi ; \
+	if [ "$(findstring _slave_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \
+		echo " slave" ; \
+	else \
+		echo " host" ; \
+	fi
+	@./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval
+
 MPC8560ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads

 MPC8541CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds

+MPC8548CDS_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds
+
 MPC8555CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds


--- a/README
+++ b/README
@@ -287,17 +287,17 @@ The following options need to be configured:
 		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_SXNI855T
 		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM823L
 		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM8260
-		CONFIG_ep8260		CONFIG_MPC8560ADS	CONFIG_TQM850L
-		CONFIG_ERIC		CONFIG_MUSENKI		CONFIG_TQM855L
-		CONFIG_ESTEEM192E	CONFIG_MVS1		CONFIG_TQM860L
-		CONFIG_ETX094		CONFIG_NETPHONE		CONFIG_TTTech
-		CONFIG_EVB64260		CONFIG_NETTA		CONFIG_UTX8245
-		CONFIG_FADS823		CONFIG_NETVIA		CONFIG_V37
-		CONFIG_FADS850SAR	CONFIG_NX823		CONFIG_W7OLMC
-		CONFIG_FADS860T		CONFIG_OCRTC		CONFIG_W7OLMG
-		CONFIG_FLAGADM		CONFIG_ORSG		CONFIG_WALNUT
-		CONFIG_FPS850L		CONFIG_OXC		CONFIG_ZPC1900
-		CONFIG_FPS860L					CONFIG_ZUMA
+		CONFIG_ep8260		CONFIG_MPC8540EVAL	CONFIG_TQM850L
+		CONFIG_ERIC		CONFIG_MPC8560ADS	CONFIG_TQM855L
+		CONFIG_ESTEEM192E	CONFIG_MUSENKI		CONFIG_TQM860L
+		CONFIG_ETX094		CONFIG_MVS1		CONFIG_TTTech
+		CONFIG_EVB64260		CONFIG_NETPHONE		CONFIG_UTX8245
+		CONFIG_FADS823		CONFIG_NETTA		CONFIG_V37
+		CONFIG_FADS850SAR	CONFIG_NETVIA		CONFIG_W7OLMC
+		CONFIG_FADS860T		CONFIG_NX823		CONFIG_W7OLMG
+		CONFIG_FLAGADM		CONFIG_OCRTC		CONFIG_WALNUT
+		CONFIG_FPS850L		CONFIG_ORSG		CONFIG_ZPC1900
+		CONFIG_FPS860L		CONFIG_OXC		CONFIG_ZUMA

 		ARM based boards:
 		-----------------
@@ -2186,14 +2186,14 @@ configurations; the following names are supported:
 	DUET_ADS_config		MBX_config		sbc8560_66_config
 	EBONY_config		MPC8260ADS_config	SM850_config
 	ELPT860_config		MPC8540ADS_config	SPD823TS_config
-	ESTEEM192E_config	MPC8560ADS_config	stxgp3_config
-	ETX094_config		NETVIA_config		SXNI855T_config
-	FADS823_config		omap1510inn_config	TQM823L_config
-	FADS850SAR_config	omap1610h2_config	TQM850L_config
-	FADS860T_config		omap1610inn_config	TQM855L_config
-	FPS850L_config		omap5912osk_config	TQM860L_config
-				omap2420h4_config	walnut_config
-							Yukon8220_config
+	ESTEEM192E_config	MPC8540EVAL_config	stxgp3_config
+	ETX094_config		MPC8560ADS_config	SXNI855T_config
+	FADS823_config		NETVIA_config		TQM823L_config
+	FADS850SAR_config	omap1510inn_config	TQM850L_config
+	FADS860T_config		omap1610h2_config	TQM855L_config
+	FPS850L_config		omap1610inn_config	TQM860L_config
+				omap5912osk_config	walnut_config
+				omap2420h4_config	Yukon8220_config
 							ZPC1900_config

 Note: for some board special configuration names may exist; check if

--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/cds/mpc8541cds/mpc8541cds.c
@@ -32,7 +32,7 @@
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"

-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif

@@ -271,7 +271,7 @@ initdram(int board_type)
 #endif
 	dram_size = spd_sdram();

-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize and enable DDR ECC.
 	 */

--- a/board/cds/mpc8541cds/u-boot.lds
+++ b/board/cds/mpc8541cds/u-boot.lds
@@ -69,7 +69,6 @@ SECTIONS
    cpu/mpc85xx/interrupts.o (.text)
    cpu/mpc85xx/cpu_init.o (.text)
    cpu/mpc85xx/cpu.o (.text)
-    cpu/mpc85xx/tsec.o (.text)
    cpu/mpc85xx/speed.o (.text)
    cpu/mpc85xx/pci.o (.text)
    common/dlmalloc.o (.text)

--- a/board/cds/mpc8548cds/Makefile
+++ b/board/cds/mpc8548cds/Makefile
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cds/mpc8548cds/config.mk
+++ b/board/cds/mpc8548cds/config.mk
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8548cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);