Commit b90c045f authored by Michal Simek's avatar Michal Simek
Browse files

synchronizition with mainline

parent 6b6f287a
......@@ -144,7 +144,7 @@ ifeq ($(ARCH),m68k)
CROSS_COMPILE = m68k-elf-
endif
ifeq ($(ARCH),microblaze)
CROSS_COMPILE = microblaze-uclinux-
CROSS_COMPILE = mb-
endif
ifeq ($(ARCH),blackfin)
CROSS_COMPILE = bfin-uclinux-
......@@ -201,9 +201,8 @@ ifeq ($(CPU),ixp)
LIBS += cpu/ixp/npe/libnpe.a
endif
LIBS += lib_$(ARCH)/lib$(ARCH).a
LIBS += fs/cramfs/libcramfs.a fs/ext2/libext2fs.a fs/fat/libfat.a \
fs/fdos/libfdos.a fs/jffs2/libjffs2.a fs/reiserfs/libreiserfs.a \
fs/romfs/libromfs.a
LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
LIBS += net/libnet.a
LIBS += disk/libdisk.a
LIBS += rtc/librtc.a
......@@ -326,14 +325,14 @@ depend dep: version
tags ctags:
ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) include \
lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
fs/cramfs fs/fat fs/fdos fs/jffs2 fs/romfs\
fs/cramfs fs/fat fs/fdos fs/jffs2 \
net disk rtc dtt drivers drivers/sk98lin common \
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
etags:
etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) include \
lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
fs/cramfs fs/fat fs/fdos fs/jffs2 fs/romfs\
fs/cramfs fs/fat fs/fdos fs/jffs2 \
net disk rtc dtt drivers drivers/sk98lin common \
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
......
......@@ -22,17 +22,32 @@
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
......
......@@ -25,8 +25,8 @@
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
#
TEXT_BASE = 0x30000000
TEXT_BASE = 0x38000000
PLATFORM_CPPFLAGS += -mxl-pattern-compare
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mcpu=v5.00.c
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift
......@@ -28,24 +28,17 @@
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 100000000
/* Microblaze is microblaze_0 */
#define XILINX_USE_MSR_INSTR 1
#define XILINX_PVR 0
#define XILINX_FSL_NUMBER 0
/* Interrupt controller is opb_intc_0 */
#define XILINX_INTC_BASEADDR 0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS 7
#define XILINX_INTC_NUM_INTR_INPUTS 11
/* Timer pheriphery is opb_timer_1 */
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 0
#define XILINX_TIMER_IRQ 1
/* Uart pheriphery is RS232_Uart_1 */
#define XILINX_UARTLITE_BASEADDR 0x40600000
#define XILINX_UARTLITE_BAUDRATE 115200
/* IIC doesn't exist */
#define XILINX_UART_BASEADDR 0x40600000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
......@@ -58,10 +51,14 @@
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
#define XILINX_EMAC_BASEADDR 0x40c00000
#define XILINX_EMAC_DMA_PRESENT 3
#define XILINX_EMAC_HALF_DUPLEX_EXIST 1
#define XILINX_EMAC_MII_EXIST 1
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
......@@ -85,7 +85,7 @@
*/
/*
* JFFS2/CRAMFS/ROMFS support
* JFFS2/CRAMFS support
*/
#include <common.h>
#include <command.h>
......@@ -175,11 +175,6 @@ extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename
extern int cramfs_ls (struct part_info *info, char *filename);
extern int cramfs_info (struct part_info *info);
extern int romfs_check (struct part_info *info);
extern int romfs_load (char *loadoffset, struct part_info *info, char *filename);
extern int romfs_ls (struct part_info *info, char *filename);
extern int romfs_info (struct part_info *info);
static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num);
/* command line only routines */
......@@ -1879,22 +1874,14 @@ int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for JFFS2, cramfs, romfs */
if (cramfs_check(part)) {
fsname = "CRAMFS";
} else if (romfs_check(part)) {
fsname = "ROMFS";
} else {
fsname = "JFFS2";
}
/* check partition type for cramfs */
fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset);
if (cramfs_check(part)) {
size = cramfs_load ((char *) offset, part, filename);
} else if (romfs_check(part)){
size = romfs_load ((char *) offset, part, filename);
} else {
/* if this is not cramfs or romfs assume jffs2 */
/* if this is not cramfs assume jffs2 */
size = jffs2_1pass_load((char *)offset, part, filename);
}
......@@ -1941,10 +1928,8 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* check partition type for cramfs */
if (cramfs_check(part)) {
ret = cramfs_ls (part, filename);
} else if (romfs_check(part)) {
ret = romfs_ls (part, filename);
} else {
/* if this is not cramfs or romfs assume jffs2 */
/* if this is not cramfs assume jffs2 */
ret = jffs2_1pass_ls(part, filename);
}
......@@ -1966,6 +1951,7 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
struct part_info *part;
char *fsname;
int ret;
/* make sure we are in sync with env variables */
......@@ -1975,17 +1961,13 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
puts("### filesystem type is ");
fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
printf("### filesystem type is %s\n", fsname);
if (cramfs_check(part)) {
puts("CRAMFS\n");
ret = cramfs_info (part);
} else if (romfs_check(part)) {
puts("ROMFS\n");
ret = romfs_info (part);
} else {
/* if this is not cramfs or romfs assume jffs2 */
puts("JFFS2\n");
/* if this is not cramfs assume jffs2 */
ret = jffs2_1pass_info(part);
}
......
......@@ -357,7 +357,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
if (argc < 2) {
if (argc < 1) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
......@@ -382,7 +382,6 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
puts ("ESR");
break;
default:
puts ("Unsupported register\n");
return 1;
}
printf (": 0x%08lx\n", val);
......@@ -409,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
" 3 - blocking control write\n");
U_BOOT_CMD (rspr, 3, 1, do_rspr,
"rspr - read/write special purpose register\n",
"rmsr - read/write special purpose register\n",
"- reg_num [write value] read/write special purpose register\n"
" 1 - MSR - Machine status register\n"
" 3 - EAR - Exception address register\n"
" 5 - ESR - Exception status register\n");
" 0 - MSR - Machine status register\n"
" 1 - EAR - Exception address register\n"
" 2 - ESR - Exception status register\n");
#endif
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
* Michal SIMEK <moonstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
......
......@@ -33,13 +33,15 @@ _start:
addi r1, r0, CFG_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
addi r6, r0, 0xb000 /* hex b000 opcode imm */
bslli r6, r6, 16 /* shift */
swi r6, r0, 0x0 /* reset address */
swi r6, r0, 0x8 /* user vector exception */
swi r6, r0, 0x10 /* interrupt */
swi r6, r0, 0x20 /* hardware exception */
addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
addi r6, r0, 0xb808 /* hew b808 opcode brai*/
bslli r6, r6, 16
swi r6, r0, 0x4 /* reset address */
swi r6, r0, 0xC /* user vector exception */
swi r6, r0, 0x14 /* interrupt */
......
......@@ -33,17 +33,10 @@ void reset_timer (void)
timestamp = 0;
}
#ifdef CFG_TIMER_0
ulong get_timer (ulong base)
{
return (timestamp - base);
}
#else
ulong get_timer (ulong base)
{
return (timestamp++ - base);
}
#endif
void set_timer (ulong t)
{
......
......@@ -24,7 +24,8 @@
include $(TOPDIR)/config.mk
LIB := $(obj)libnet.a
COBJS := mcffec.o xilinx_emac.o xilinx_emaclite.o
COBJS := mcffec.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
......
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on Xilinx drivers
*
*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <asm/io.h>
#include "xilinx_emac.h"
#ifdef XILINX_EMAC
#undef DEBUG
#define ENET_MAX_MTU PKTSIZE
#define ENET_ADDR_LENGTH 6
static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
static xemac emac;
void eth_halt(void)
{
#ifdef DEBUG
puts ("eth_halt\n");
#endif
}
int eth_init(bd_t * bis)
{
u32 helpreg;
#ifdef DEBUG
printf("EMAC Initialization Started\n\r");
#endif
if (emac.isstarted) {
puts("Emac is started\n");
return 0;
}
memset (&emac, 0, sizeof (xemac));
emac.baseaddress = XILINX_EMAC_BASEADDR;
/* Setting up FIFOs */
emac.recvfifo.regbaseaddress = emac.baseaddress +
XEM_PFIFO_RXREG_OFFSET;
emac.recvfifo.databaseaddress = emac.baseaddress +
XEM_PFIFO_RXDATA_OFFSET;
out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
emac.sendfifo.regbaseaddress = emac.baseaddress +
XEM_PFIFO_TXREG_OFFSET;
emac.sendfifo.databaseaddress = emac.baseaddress +
XEM_PFIFO_TXDATA_OFFSET;
out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
/* Reset the entire IPIF */
out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
XIIF_V123B_RESET_MASK);
/* Stopping EMAC for setting up MAC */
helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
if (!getenv("ethaddr")) {
memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
}
/* Set the device station address high and low registers */
helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
(bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
emac.isstarted = 1;
/* Enable the transmitter, and receiver */
helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
printf("EMAC Initialization complete\n\r");
return 0;
}
int eth_send(volatile void *ptr, int len)
{
u32 intrstatus;
u32 xmitstatus;
u32 fifocount;
u32 wordcount;
u32 extrabytecount;
u32 *wordbuffer = (u32 *) ptr;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
/*
* Check for overruns and underruns for the transmit status and length
* FIFOs and make sure the send packet FIFO is not deadlocked.
* Any of these conditions is bad enough that we do not want to
* continue. The upper layer software should reset the device to resolve
* the error.
*/
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
#ifdef DEBUG
puts ("Transmitting overrun error\n");
#endif
return 0;
} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
#ifdef DEBUG
puts ("Transmitting underrun error\n");
#endif
return 0;
} else if (in_be32 (emac.sendfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
#ifdef DEBUG
puts("Transmitting fifo error\n");
#endif
return 0;
}
/*
* Before writing to the data FIFO, make sure the length FIFO is not
* full. The data FIFO might not be full yet even though the length FIFO
* is. This avoids an overrun condition on the length FIFO and keeps the
* FIFOs in sync.
*
* Clear the latched LFIFO_FULL bit so next time around the most
* current status is represented
*/
if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
#ifdef DEBUG
puts ("Fifo is full\n");
#endif
return 0;
}
/* get the count of how many words may be inserted into the FIFO */
fifocount = in_be32 (emac.sendfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
wordcount = len >> 2;
extrabytecount = len & 0x3;
if (fifocount < wordcount) {
#ifdef DEBUG
puts ("Sending packet is larger then size of FIFO\n");
#endif
return 0;
}
for (fifocount = 0; fifocount < wordcount; fifocount++) {
out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
}
if (extrabytecount > 0) {
u32 lastword = 0;
u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
if (extrabytecount == 1) {
lastword = extrabytesbuffer[0] << 24;
} else if (extrabytecount == 2) {
lastword = extrabytesbuffer[0] << 24 |
extrabytesbuffer[1] << 16;
} else if (extrabytecount == 3) {
lastword = extrabytesbuffer[0] << 24 |
extrabytesbuffer[1] << 16 |
extrabytesbuffer[2] << 8;
}
out_be32 (emac.sendfifo.databaseaddress, lastword);
}
/* Loop on the MAC's status to wait for any pause to complete */
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
intrstatus = in_be32 ((emac.baseaddress) +
XIIF_V123B_IISR_OFFSET);
/* Clear the pause status from the transmit status register */
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
}
/*
* Set the MAC's transmit packet length register to tell it to transmit
*/
out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
/*
* Loop on the MAC's status to wait for the transmit to complete.
* The transmit status is in the FIFO when the XMIT_DONE bit is set.
*/
do {
intrstatus = in_be32 ((emac.baseaddress) +
XIIF_V123B_IISR_OFFSET);
}
while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
#ifdef DEBUG
puts ("Transmitting overrun error\n");
#endif
return 0;
} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
#ifdef DEBUG
puts ("Transmitting underrun error\n");
#endif
return 0;
}
/* Clear the interrupt status register of transmit statuses */
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_ALL_MASK);
/*
* Collision errors are stored in the transmit status register
* instead of the interrupt status register
*/
if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
(xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
#ifdef DEBUG
puts ("Transmitting collision error\n");
#endif
return 0;
}
return 1;
}
int eth_rx(void)
{
u32 pktlength;
u32 intrstatus;
u32 fifocount;
u32 wordcount;
u32 extrabytecount;
u32 lastword;
u8 *extrabytesbuffer;
if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
& XPF_DEADLOCK_MASK) {
out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
#ifdef DEBUG
puts ("Receiving FIFO deadlock\n");
#endif
return 0;
}
/*
* Get the interrupt status to know what happened (whether an error
* occurred and/or whether frames have been received successfully).
* When clearing the intr status register, clear only statuses that
* pertain to receive.
*/
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
/*
* Before reading from the length FIFO, make sure the length FIFO is not
* empty. We could cause an underrun error if we try to read from an
* empty FIFO.
*/
if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
#ifdef DEBUG
/* puts("Receiving FIFO is empty\n"); */
#endif
return 0;
}
/*
* Determine, from the MAC, the length of the next packet available
* in the data FIFO (there should be a non-zero length here)
*/
pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
if (!pktlength) {