Commit ba5dfc11 authored by Benoît Thébaudeau's avatar Benoît Thébaudeau Committed by Stefano Babic
Browse files

imx: mx5: Remove legacy iomux support



Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.
Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
parent 3fec2c67
......@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o iomux.o
COBJS = soc.o clock.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
......
/*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
/* IOMUX register (base) addresses */
enum iomux_reg_addr {
IOMUXGPR0 = IOMUXC_BASE_ADDR,
IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
};
#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
/* Get the iomux register address of this pin */
static inline u32 get_mux_reg(iomux_pin_name_t pin)
{
u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
* i.MX51 TO1 has offset with the register
* which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
(pin == MX51_PIN_NANDF_RB7))
; /* Do nothing */
else if (mux_reg >= 0x2FC)
mux_reg += 8;
else if (mux_reg >= 0x130)
mux_reg += 0xC;
}
#endif
mux_reg += IOMUXSW_MUX_CTL;
return mux_reg;
}
/* Get the pad register address of this pin */
static inline u32 get_pad_reg(iomux_pin_name_t pin)
{
u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
* i.MX51 TO1 has offset with the register
* which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
(pin == MX51_PIN_NANDF_RB7))
; /* Do nothing */
else if (pad_reg == 0x4D0 - PAD_I_START)
pad_reg += 0x4C;
else if (pad_reg == 0x860 - PAD_I_START)
pad_reg += 0x9C;
else if (pad_reg >= 0x804 - PAD_I_START)
pad_reg += 0xB0;
else if (pad_reg >= 0x7FC - PAD_I_START)
pad_reg += 0xB4;
else if (pad_reg >= 0x4E4 - PAD_I_START)
pad_reg += 0xCC;
else
pad_reg += 8;
}
#endif
pad_reg += IOMUXSW_PAD_CTL;
return pad_reg;
}
/* Get the last iomux register address */
static inline u32 get_mux_end(void)
{
#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0)
return IOMUXC_BASE_ADDR + (0x3F8 - 4);
else
return IOMUXC_BASE_ADDR + (0x3F0 - 4);
#endif
return IOMUXSW_MUX_END;
}
/*
* This function is used to configure a pin through the IOMUX module.
* @param pin a pin number as defined in iomux_pin_name_t
* @param cfg an output function as defined in iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
u32 mux_reg = get_mux_reg(pin);
if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
return ;
if (cfg == IOMUX_CONFIG_GPIO)
writel(PIN_TO_ALT_GPIO(pin), mux_reg);
else
writel(cfg, mux_reg);
}
/*
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by iomux_pin_name_t
* @param cfg an input function as defined in iomux_pin_cfg_t
*
*/
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
iomux_config_mux(pin, cfg);
}
/*
* Release ownership for an IO pin
*
* @param pin a name defined by iomux_pin_name_t
* @param cfg an input function as defined in iomux_pin_cfg_t
*/
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
}
/*
* This function configures the pad value for a IOMUX pin.
*
* @param pin a pin number as defined in iomux_pin_name_t
* @param config the ORed value of elements defined in iomux_pad_config_t
*/
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
{
u32 pad_reg = get_pad_reg(pin);
writel(config, pad_reg);
}
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
{
u32 pad_reg = get_pad_reg(pin);
return readl(pad_reg);
}
/*
* This function configures daisy-chain
*
* @param input index of input select register
* @param config the binary value of elements
*/
void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
{
u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
writel(config, reg);
}
/*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MACH_MX5_IOMUX_H__
#define __MACH_MX5_IOMUX_H__
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
typedef unsigned int iomux_pin_name_t;
/* various IOMUX output functions */
typedef enum iomux_config {
IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
} iomux_pin_cfg_t;
/* various IOMUX pad functions */
typedef enum iomux_pad_config {
PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */
PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */
PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */
PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */
PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */
PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */
PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */
PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */
PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */
PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */
PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */
PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */
PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */
PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */
PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */
PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */
PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */
PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
} iomux_pad_config_t;
/* various IOMUX input functions */
typedef enum iomux_input_config {
INPUT_CTL_PATH0 = 0x0,
INPUT_CTL_PATH1,
INPUT_CTL_PATH2,
INPUT_CTL_PATH3,
INPUT_CTL_PATH4,
INPUT_CTL_PATH5,
INPUT_CTL_PATH6,
INPUT_CTL_PATH7,
} iomux_input_config_t;
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
#endif /* __MACH_MX5_IOMUX_H__ */
This diff is collapsed.
......@@ -21,8 +21,6 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include "ehci.h"
......@@ -87,77 +85,6 @@
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
/* USB pin configuration */
#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
#ifdef CONFIG_MX51
/*
* Configure the MX51 USB H1 IOMUX
*/
void setup_iomux_usb_h1(void)
{
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
}
/*
* Configure the MX51 USB H2 IOMUX
*/
void setup_iomux_usb_h2(void)
{
mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
}
#endif
int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
......
......@@ -277,10 +277,4 @@ struct usb_ehci {
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
/* CPU-specific abstracted-out IOMUX init */
#ifdef CONFIG_MX51
void setup_iomux_usb_h1(void);
void setup_iomux_usb_h2(void);
#endif
#endif /* _EHCI_FSL_H */
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