Commit bbea46f7 authored by Kim Phillips's avatar Kim Phillips
Browse files

mpc83xx: implement board_add_ram_info



add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:

DRAM:  256 MB (DDR1, 64-bit, ECC on)

and for boards with SDRAM on the local bus, a line such as this is
added:

SDRAM: 64 MB (local bus)

also replaced some magic numbers with their equivalent define names.
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
parent 14778585
......@@ -91,8 +91,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
puts("\n DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
......
......@@ -112,8 +112,6 @@ long int initdram(int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
puts("Initializing\n");
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
......@@ -127,7 +125,6 @@ long int initdram(int board_type)
resume_from_sleep();
#endif
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return msize;
}
......@@ -114,8 +114,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
puts("\n DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
......
......@@ -70,8 +70,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
puts("Initializing\n");
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
......@@ -90,7 +88,7 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
......@@ -191,9 +189,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
......@@ -255,7 +250,6 @@ void sdram_init(void)
#else
void sdram_init(void)
{
puts(" SDRAM on Local Bus is NOT available!\n");
}
#endif
......
......@@ -76,7 +76,7 @@ int fixed_sdram(void)
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
......@@ -162,7 +162,6 @@ long int initdram(int board_type)
ddr_enable_ecc(msize * 1048576);
#endif
puts(" DDR RAM: ");
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
......
......@@ -149,7 +149,7 @@ long int initdram(int board_type)
* Initialize SDRAM if it is on local bus.
*/
sdram_init();
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
......@@ -234,8 +234,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc = &immap->lbus;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
......@@ -291,7 +289,6 @@ void sdram_init(void)
#else
void sdram_init(void)
{
puts("SDRAM on Local Bus is NOT available!\n");
}
#endif
......
......@@ -64,8 +64,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
puts("Initializing\n");
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
......@@ -84,7 +82,6 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
......@@ -130,7 +127,7 @@ int fixed_sdram(void)
#if defined(CONFIG_DDR_2T_TIMING)
| SDRAM_CFG_2T_EN
#endif
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
| SDRAM_CFG_SDRAM_TYPE_DDR1;
#if defined (CONFIG_DDR_32BIT)
/* for 32-bit mode burst length is 8 */
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
......
......@@ -114,7 +114,7 @@ long int initdram (int board_type)
/* enable DDR controller */
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
SDRAM_CFG_SREN |
SDRAM_CFG_SDRAM_TYPE_DDR);
SDRAM_CFG_SDRAM_TYPE_DDR1);
SYNC;
/* size detection */
......@@ -388,7 +388,7 @@ static void set_ddr_config(void) {
/* don't enable DDR controller yet */
im->ddr.sdram_cfg =
SDRAM_CFG_SREN |
SDRAM_CFG_SDRAM_TYPE_DDR;
SDRAM_CFG_SDRAM_TYPE_DDR1;
SYNC;
/* Set SDRAM mode */
......
......@@ -34,6 +34,30 @@
#include <asm/mmu.h>
#include <spd_sdram.h>
void board_add_ram_info(int use_default)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
puts(", 32-bit");
else
puts(", 64-bit");
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
puts(", ECC on)");
else
puts(", ECC off)");
#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
#endif
}
#ifdef CONFIG_SPD_EEPROM
DECLARE_GLOBAL_DATA_PTR;
......@@ -109,7 +133,7 @@ long int spd_sdram()
unsigned int n_ranks;
unsigned int odt_rd_cfg, odt_wr_cfg;
unsigned char twr_clk, twtr_clk;
unsigned char sdram_type;
unsigned int sdram_type;
unsigned int memsize;
unsigned int law_size;
unsigned char caslat, caslat_ctrl;
......@@ -137,7 +161,7 @@ long int spd_sdram()
#endif
/* Check the memory type */
if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
printf("DDR: Module mem type is %02X\n", spd.mem_type);
debug("DDR: Module mem type is %02X\n", spd.mem_type);
return 0;
}
......@@ -578,17 +602,17 @@ long int spd_sdram()
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
else
burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
printf("\n DDR DIMM: data bus width is 32 bit");
debug("\n DDR DIMM: data bus width is 32 bit");
} else {
burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
printf("\n DDR DIMM: data bus width is 64 bit");
debug("\n DDR DIMM: data bus width is 64 bit");
}
/* Is this an ECC DDR chip? */
if (spd.config == 0x02)
printf(" with ECC\n");
debug(" with ECC\n");
else
printf(" without ECC\n");
debug(" without ECC\n");
/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
Burst type is sequential
......@@ -718,26 +742,26 @@ long int spd_sdram()
* sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
*/
if (spd.mem_type == SPD_MEMTYPE_DDR)
sdram_type = 2;
sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
else
sdram_type = 3;
sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
sdram_cfg = (0
| (1 << 31) /* DDR enable */
| (1 << 30) /* Self refresh */
| (sdram_type << 24) /* SDRAM type */
| SDRAM_CFG_MEM_EN /* DDR enable */
| SDRAM_CFG_SREN /* Self refresh */
| sdram_type /* SDRAM type */
);
/* sdram_cfg[3] = RD_EN - registered DIMM enable */
if (spd.mod_attr & 0x02)
sdram_cfg |= 0x10000000;
sdram_cfg |= SDRAM_CFG_RD_EN;
/* The DIMM is 32bit width */
if (spd.dataw_lsb == 0x20) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
sdram_cfg |= 0x000C0000;
sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
if (spd.mem_type == SPD_MEMTYPE_DDR2)
sdram_cfg |= 0x00080000;
sdram_cfg |= SDRAM_CFG_32_BE;
}
ddrc_ecc_enable = 0;
......@@ -758,7 +782,7 @@ long int spd_sdram()
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
#if defined(CONFIG_DDR_2T_TIMING)
/*
......
......@@ -113,12 +113,12 @@
/* 0x03200064 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32 )
#else
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#endif
......
......@@ -705,8 +705,9 @@
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
#define SDRAM_CFG_SDRAM_TYPE 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_32_BE 0x00080000
......
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