Commit bbeff30c authored by Stefan Roese's avatar Stefan Roese
Browse files

ppc4xx: Remove superfluous dram_init() call or replace it by initdram()



Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.

This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:

csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG

I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.
Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent 192f90e2
......@@ -33,14 +33,6 @@
extern void board_pll_init_f(void);
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
......@@ -116,10 +108,3 @@ long int initdram(int board_type)
return (CFG_MBYTES_RAM << 20);
}
#ifndef CONFIG_NAND_SPL
int testdram(void)
{
return (0);
}
#endif
......@@ -66,14 +66,6 @@ int checkboard(void)
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
......@@ -85,11 +77,3 @@ long int initdram(int board_type)
ret = spd_sdram();
return ret;
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}
......@@ -351,8 +351,3 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
void sdram_init(void)
{
return;
}
......@@ -85,14 +85,6 @@ int checkboard(void)
return (0);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/*
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
......@@ -101,11 +93,3 @@ long int initdram(int board_type)
{
return spd_sdram();
}
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("test: xxx MB - ok\n");
return (0);
}
......@@ -200,7 +200,7 @@ int checkboard(void)
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
* initdram -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
......@@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
void sdram_init(void)
long int initdram(int board)
{
register uint reg;
int tr1_bank1, tr1_bank2;
......@@ -327,57 +327,11 @@ void sdram_init(void)
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
......
......@@ -28,7 +28,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
......@@ -134,14 +134,3 @@ ext_bus_cntlr_init:
mtdcr ebccfgd,r4
blr
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: Configures SDRAM memory banks. */
/* NOTE: for CrayL1 we have ECC memory, so enable it. */
/*....now done in C in L1.c:init_sdram for readability. */
/*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
......@@ -27,6 +27,8 @@
#include <miiphy.h>
#include <ppc4xx_enet.h>
void sdram_init(void);
/*
* Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
*
......@@ -124,6 +126,13 @@ long initdram (int board_type)
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
......
......@@ -27,6 +27,8 @@
#include <miiphy.h>
#include <ppc4xx_enet.h>
void sdram_init(void);
/*
* board_early_init_f: do early board initialization
*
......@@ -92,6 +94,13 @@ long initdram (int board_type)
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
......
......@@ -31,6 +31,8 @@
#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
void sdram_init(void);
int board_early_init_f (void)
{
......@@ -127,6 +129,12 @@ long int initdram (int board_type)
int TotalSize;
#endif
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
#ifdef CONFIG_ERIC
/*
......
......@@ -190,28 +190,6 @@ int checkboard (void)
return 0;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#if 1 /* test-only: some internal test routines... */
/*
......
......@@ -181,22 +181,3 @@ int checkboard (void)
return 0;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
return (16 * 1024 * 1024);
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
......@@ -3,6 +3,8 @@
#include <common.h>
#include "exbitgen.h"
void sdram_init(void);
/* ************************************************************************ */
int board_early_init_f (void)
/* ------------------------------------------------------------------------ --
......@@ -83,6 +85,13 @@ long int initdram (int board_type)
ulong bank_size;
ulong tmp;
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
......
......@@ -149,41 +149,6 @@ long int initdram (int board_type)
}
#if 1 /* test-only */
void sdram_init(void)
{
init_sdram_static_settings();
}
#endif
#if 0 /* test-only */
long int initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
#endif
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
......
......@@ -93,13 +93,3 @@ ext_bus_cntlr_init:
mtdcr ebccfgd,r4
blr
/*----------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: This function is called by cpu/ppc4xx/start.S code */
/* to get the SDRAM initialized. */
/*----------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
......@@ -28,7 +28,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
......@@ -178,19 +178,6 @@ ext_bus_cntlr_init:
nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------
* Function: sdram_init
* Description: Configures the internal SRAM memory. and setup the
* Stackpointer in it.
*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
#if defined(CONFIG_BOOT_PCI)
.section .bootpg,"ax"
.globl _start_pci
......
......@@ -175,19 +175,6 @@
nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------
* Function: sdram_init
* Description: Configures the internal SRAM memory. and setup the
* Stackpointer in it.
*----------------------------------------------------------------------------- */
.globl sdram_init
sdram_init:
blr
#if defined(CONFIG_BOOT_PCI)
.section .bootpg,"ax"
.globl _start_pci
......
......@@ -120,15 +120,6 @@ void hcu_led_set(u32 value)
out_be32((u32 *)GPIO0_OR, tmp);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram or initdram
* used for HCUx
*/
void sdram_init(void)
{
return;
}
/*
* hcu_get_slot
*/
......
......@@ -40,28 +40,6 @@
void hcu_led_set(u32 value);
void dcbz_area(u32 start_address, u32 num_bytes);
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define ECC_RAM 0x03267F0B
#define NO_ECC_RAM 0x00267F0B
......@@ -111,11 +89,11 @@ static int wait_for_dlllock(void)
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_17);
mtdcr(memcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
val = mfdcr(memcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) ==
DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
......
......@@ -127,15 +127,6 @@ void hcu_led_set(u32 value)
out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value);
}
/*
* sdram_init - Dummy implementation for start.S, spd_sdram or initdram
* used for HCUx
*/
void sdram_init(void)
{
return;
}
/*
* hcu_get_slot
*/
......
......@@ -31,6 +31,7 @@
#include <watchdog.h>
unsigned long get_dram_size (void);
void sdram_init(void);
/*
* Macros to transform values
......@@ -153,6 +154,13 @@ int checkboard (void)
long int initdram (int board_type)
{
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
* in cpu/ppc4xx
*/
sdram_init();
return get_dram_size ();
}
......
......@@ -42,7 +42,3 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
......@@ -164,7 +164,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
/*
* Autodetect onboard SDRAM on 405 platforms
*/
void sdram_init(void)
long int initdram(int board_type)
{
ulong speed;
ulong sdtr1;
......@@ -232,9 +232,15 @@ void sdram_init(void)
mtsdram(mem_mcopt1, 0);
}
#endif
return;
/*
* OK, size detected -> all done
*/
return mb0cf[i].size;
}
}
return 0;
}
#else /* CONFIG_440 */
......
......@@ -217,7 +217,6 @@
.extern ext_bus_cntlr_init
.extern sdram_init
#ifdef CONFIG_NAND_U_BOOT
.extern reconfig_tlb0
#endif
......@@ -1119,11 +1118,6 @@ _start:
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CFG_INIT_DCACHE_CS */
/*----------------------------------------------------------------------- */
/* Initialize SDRAM Controller */
/*----------------------------------------------------------------------- */
bl sdram_init
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
......
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