Commit c178d3da authored by wdenk's avatar wdenk
Browse files

* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):

  see doc/README.MPC866 for details;
  implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
  calculate CPU clock frequency from PLL register values.

* Add support for 128 MB RAM on TQM8xxL/M modules
parent ef978730
......@@ -2,6 +2,13 @@
Changes since U-Boot 1.0.1:
======================================================================
* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
see doc/README.MPC866 for details;
implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
calculate CPU clock frequency from PLL register values.
* Add support for 128 MB RAM on TQM8xxL/M modules
* Fix PS/2 keyboard problem caused by statically initialized variable
pointing to a location in flash
......
......@@ -483,11 +483,7 @@ TQM862M_config \
TQM862M_66MHz_config \
TQM862M_80MHz_config \
TQM862M_100MHz_config \
TQM866M_config \
TQM866M_66MHz_config \
TQM866M_80MHz_config \
TQM866M_100MHz_config \
TQM866M_133MHz_config: unconfig
TQM866M_config: unconfig
@ >include/config.h
@[ -z "$(findstring _66MHz,$@)" ] || \
{ echo "#define CONFIG_66MHz" >>include/config.h ; \
......
......@@ -3158,7 +3158,7 @@ Please note that U-Boot is implemented in C (and to some small parts
in Assembler); no C++ is used, so please do not use C++ style
comments (//) in your code.
Please also stick to the following formatiing rules:
Please also stick to the following formatting rules:
- remove any trailing white space
- use TAB characters for indentation, not spaces
- make sure NOT to use DOS '\r\n' line feeds
......
......@@ -128,6 +128,14 @@ int checkboard (void)
break;
putc (*s);
}
#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
printf (" [%d.%d...%d.%d MHz]",
CFG_866_CPUCLK_MIN / 1000000,
((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
CFG_866_CPUCLK_MAX / 1000000,
((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
);
#endif
putc ('\n');
return (0);
......@@ -139,7 +147,7 @@ long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9;
long int size8, size9, size10;
long int size_b0 = 0;
long int size_b1 = 0;
......@@ -228,9 +236,26 @@ long int initdram (int board_type)
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
if (size8 < size9) { /* leave configuration at 9 columns */
udelay(1000);
#if defined(CFG_MAMR_10COL)
/*
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;
#endif /* CFG_MAMR_10COL */
if ((size8 < size10) && (size9 < size10)) {
size_b0 = size10;
} else if ((size8 < size9) && (size10 < size9)) {
size_b0 = size9;
} else { /* back to 8 columns */
memctl->memc_mamr = CFG_MAMR_9COL;
udelay (500);
} else {
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay (500);
......@@ -272,18 +297,15 @@ long int initdram (int board_type)
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br3 =
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b0 > 0) {
/*
* Position Bank 0 immediately above Bank 1
*/
memctl->memc_or2 =
((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 =
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b1;
memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b1;
} else {
unsigned long reg;
......
......@@ -32,16 +32,17 @@ OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
fec.o i2c.o interrupts.o lcd.o scc.o \
serial.o speed.o spi.o \
traps.o upatch.o video.o
SOBJS = plprcr_write.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS) kgdb.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS) kgdb.o
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@
sinclude .depend
......
......@@ -42,7 +42,9 @@ void cpu_init_f (volatile immap_t * immr)
{
#ifndef CONFIG_MBX
volatile memctl8xx_t *memctl = &immr->im_memctl;
# ifdef CFG_PLPRCR
ulong mfmask;
# endif
#endif
ulong reg;
......@@ -92,6 +94,7 @@ void cpu_init_f (volatile immap_t * immr)
*
* For newer (starting MPC866) chips PLPRCR layout is different.
*/
#ifdef CFG_PLPRCR
if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
mfmask = PLPRCR_MFACT_MSK;
else
......@@ -105,6 +108,7 @@ void cpu_init_f (volatile immap_t * immr)
reg |= CFG_PLPRCR; /* reset control bits */
}
immr->im_clkrst.car_plprcr = reg;
#endif
/*
* Memory Controller:
......
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <mpc8xx.h>
#include <ppc_asm.tmpl>
#include <asm/cache.h>
#define CACHE_CMD_ENABLE 0x02000000
#define CACHE_CMD_DISABLE 0x04000000
#define CACHE_CMD_LOAD_LOCK 0x06000000
#define CACHE_CMD_UNLOCK_LINE 0x08000000
#define CACHE_CMD_UNLOCK_ALL 0x0A000000
#define CACHE_CMD_INVALIDATE 0x0C000000
#define SPEED_PLPRCR_WAIT_5CYC 150
#define _CACHE_ALIGN_SIZE 16
.text
.align 2
.globl plprcr_write_866
/*
* void plprcr_write_866 (long plprcr)
* Write PLPRCR, including workaround for device errata SIU4 and SIU9.
*/
plprcr_write_866:
mfspr r10, LR /* save the Link Register value */
/* turn instruction cache on (no MMU required for instructions)
*/
lis r4, CACHE_CMD_ENABLE@h
ori r4, r4, CACHE_CMD_ENABLE@l
mtspr IC_CST, r4
isync
/* clear IC_CST error bits
*/
mfspr r4, IC_CST
bl plprcr_here
plprcr_here:
mflr r5
/* calculate relocation offset
*/
lis r4, plprcr_here@h
ori r4, r4, plprcr_here@l
sub r5, r5, r4
/* calculate first address of this function
*/
lis r6, plprcr_write_866@h
ori r6, r6, plprcr_write_866@l
add r6, r6, r5
/* calculate end address of this function
*/
lis r7, plprcr_end@h
ori r7, r7, plprcr_end@l
add r7, r7, r5
/* load and lock code addresses
*/
mr r5, r6
plprcr_loop:
mtspr IC_ADR, r5
addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */
lis r4, CACHE_CMD_LOAD_LOCK@h
ori r4, r4, CACHE_CMD_LOAD_LOCK@l
mtspr IC_CST, r4
isync
cmpw r5, r7
blt plprcr_loop
/* IC_CST error bits not evaluated
*/
/* switch PLPRCR
*/
mfspr r4, IMMR /* read IMMR */
rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
/* write sequence according to MPC866 Errata
*/
stw r3, PLPRCR(r4)
isync
lis r3, SPEED_PLPRCR_WAIT_5CYC@h
ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l
plprcr_wait:
cmpwi r3, 0
beq plprcr_wait_end
nop
subi r3, r3, 1
b plprcr_wait
plprcr_wait_end:
/* turn instruction cache off
*/
lis r4, CACHE_CMD_UNLOCK_ALL@h
ori r4, r4, CACHE_CMD_UNLOCK_ALL@l
mtspr IC_CST, r4
isync
lis r4, CACHE_CMD_INVALIDATE@h
ori r4, r4, CACHE_CMD_INVALIDATE@l
mtspr IC_CST, r4
isync
lis r4, CACHE_CMD_DISABLE@h
ori r4, r4, CACHE_CMD_DISABLE@l
mtspr IC_CST, r4
isync
mtspr LR, r10 /* restore original Link Register value */
blr
plprcr_end:
......@@ -25,6 +25,8 @@
#include <mpc8xx.h>
#include <asm/processor.h>
#ifndef CONFIG_TQM866M
#define PITC_SHIFT 16
#define PITR_SHIFT 16
/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
......@@ -203,4 +205,117 @@ int get_clocks (void)
return (0);
}
#else /* CONFIG_MPC866_et_al */
static long init_pll_866 (long clk);
/* This function sets up PLL (init_pll_866() is called) and
* fills gd->cpu_clk and gd->bus_clk according to the environment
* variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk'
* contains invalid value).
* This functions requires an MPC866 series CPU.
*/
int get_clocks_866 (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
char tmp[64];
long cpuclk = 0;
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk))
cpuclk = CFG_866_CPUCLK_DEFAULT;
gd->cpu_clk = init_pll_866 (cpuclk);
if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
gd->bus_clk = gd->cpu_clk;
else
gd->bus_clk = gd->cpu_clk / 2;
return (0);
}
/* Adjust sdram refresh rate to actual CPU clock.
*/
int sdram_adjust_866 (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
long mamr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
return (0);
}
/* Configure PLL for MPC866/859 CPU series
* PLL multiplication factor is set to the value nearest to the desired clk,
* assuming a oscclk of 10 MHz.
*/
static long init_pll_866 (long clk)
{
extern void plprcr_write_866 (long);
volatile immap_t *immr = (immap_t *) CFG_IMMR;
long n, plprcr;
char mfi, mfn, mfd, s, pdf;
long step_mfi, step_mfn;
pdf = 0;
if (clk < 80000000) {
s = 1;
step_mfi = CFG_866_OSCCLK / 2;
mfd = 14;
step_mfn = CFG_866_OSCCLK / 30;
} else {
s = 0;
step_mfi = CFG_866_OSCCLK;
mfd = 29;
step_mfn = CFG_866_OSCCLK / 30;
}
/* Calculate integer part of multiplication factor
*/
n = clk / step_mfi;
mfi = (char)n;
/* Calculate numerator of fractional part of multiplication factor
*/
n = clk - (n * step_mfi);
mfn = (char)(n / step_mfn);
/* Calculate effective clk
*/
n = (mfi * step_mfi) + (mfn * step_mfn);
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
| PLPRCR_MFD_MSK | PLPRCR_S_MSK
| PLPRCR_MFI_MSK | PLPRCR_DBRMO))
| (mfn << PLPRCR_MFN_SHIFT)
| (mfd << PLPRCR_MFD_SHIFT)
| (s << PLPRCR_S_SHIFT)
| (mfi << PLPRCR_MFI_SHIFT)
| (pdf << PLPRCR_PDF_SHIFT);
if( (mfn > 0) && ((mfd / mfn) > 10) )
plprcr |= PLPRCR_DBRMO;
plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
immr->im_clkrstk.cark_plprcrk = 0x00000000;
return (n);
}
#endif /* CONFIG_MPC866_et_al */
/* ------------------------------------------------------------------------- */
......@@ -355,6 +355,8 @@ int serial_tstc (void);
/* $(CPU)/speed.c */
int get_clocks (void);
int get_clocks_866 (void);
int sdram_adjust_866 (void);
#if defined(CONFIG_8260)
int prt_8260_clks (void);
#endif
......
......@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
......@@ -36,27 +36,32 @@
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
#define CFG_8XX_XIN 10000000 /* XXX XXX XXX */
#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
#define CFG_866_CPUCLK_MIN 40000000 /* 40 MHz - CPU minimum clock */
#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
#define CFG_866_CPUCLK_DEFAULT 100000000 /* 100 MHz - CPU default clock */
/* (it will be used if there is no */
/* 'cpuclk' variable with valid value) */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
......@@ -81,13 +86,13 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
#define CFG_I2C_SLAVE 0xFE
......@@ -104,14 +109,14 @@
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
......@@ -120,7 +125,7 @@
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
......@@ -136,31 +141,31 @@
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if 0
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
......@@ -178,28 +183,28 @@
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
......@@ -210,10 +215,10 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
......@@ -223,7 +228,7 @@
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
/*-----------------------------------------------------------------------
......@@ -252,7 +257,7 @@
*-----------------------------------------------------------------------