Commit c292adae authored by Albert ARIBAUD's avatar Albert ARIBAUD
Browse files

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

parents a7f99bf1 4c97f169
...@@ -424,6 +424,9 @@ config OMAP54XX ...@@ -424,6 +424,9 @@ config OMAP54XX
config RMOBILE config RMOBILE
bool "Renesas ARM SoCs" bool "Renesas ARM SoCs"
config TARGET_CM_FX6
bool "Support cm_fx6"
config TARGET_S5P_GONI config TARGET_S5P_GONI
bool "Support s5p_goni" bool "Support s5p_goni"
...@@ -579,6 +582,7 @@ source "board/cirrus/edb93xx/Kconfig" ...@@ -579,6 +582,7 @@ source "board/cirrus/edb93xx/Kconfig"
source "board/cm4008/Kconfig" source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig" source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig" source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig" source "board/davedenx/qong/Kconfig"
......
...@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable) ...@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable)
} }
#endif #endif
#ifdef CONFIG_NAND_MXS
void setup_gpmi_io_clk(u32 cfg)
{
/* Disable clocks per ERR007177 from MX6 errata */
clrbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
}
#endif
void enable_usboh3_clk(unsigned char enable) void enable_usboh3_clk(unsigned char enable)
{ {
u32 reg; u32 reg;
...@@ -49,6 +78,67 @@ void enable_usboh3_clk(unsigned char enable) ...@@ -49,6 +78,67 @@ void enable_usboh3_clk(unsigned char enable)
} }
#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
void enable_enet_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
if (enable)
setbits_le32(&imx_ccm->CCGR1, mask);
else
clrbits_le32(&imx_ccm->CCGR1, mask);
}
#endif
#ifdef CONFIG_MXC_UART
void enable_uart_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
if (enable)
setbits_le32(&imx_ccm->CCGR5, mask);
else
clrbits_le32(&imx_ccm->CCGR5, mask);
}
#endif
#ifdef CONFIG_SPI
/* spi_num can be from 0 - 4 */
int enable_cspi_clock(unsigned char enable, unsigned spi_num)
{
u32 mask;
if (spi_num > 4)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
if (enable)
setbits_le32(&imx_ccm->CCGR1, mask);
else
clrbits_le32(&imx_ccm->CCGR1, mask);
return 0;
}
#endif
#ifdef CONFIG_MMC
int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
{
u32 mask;
if (bus_num > 3)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
if (enable)
setbits_le32(&imx_ccm->CCGR6, mask);
else
clrbits_le32(&imx_ccm->CCGR6, mask);
return 0;
}
#endif
#ifdef CONFIG_SYS_I2C_MXC #ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0 - 2 */ /* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num) int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
...@@ -509,6 +599,7 @@ int enable_pcie_clock(void) ...@@ -509,6 +599,7 @@ int enable_pcie_clock(void)
struct anatop_regs *anatop_regs = struct anatop_regs *anatop_regs =
(struct anatop_regs *)ANATOP_BASE_ADDR; (struct anatop_regs *)ANATOP_BASE_ADDR;
struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 lvds1_clk_sel;
/* /*
* Here be dragons! * Here be dragons!
...@@ -518,17 +609,25 @@ int enable_pcie_clock(void) ...@@ -518,17 +609,25 @@ int enable_pcie_clock(void)
* marked as ANATOP_MISC1 is actually documented in the PMU section * marked as ANATOP_MISC1 is actually documented in the PMU section
* of the datasheet as PMU_MISC1. * of the datasheet as PMU_MISC1.
* *
* Switch LVDS clock source to SATA (0xb), disable clock INPUT and * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
* enable clock OUTPUT. This is important for PCI express link that * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
* is clocked from the i.MX6. * for PCI express link that is clocked from the i.MX6.
*/ */
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
if (is_cpu_type(MXC_CPU_MX6SX))
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
else
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
clrsetbits_le32(&anatop_regs->ana_misc1, clrsetbits_le32(&anatop_regs->ana_misc1,
ANADIG_ANA_MISC1_LVDSCLK1_IBEN | ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
/* PCIe reference clock sourced from AXI. */ /* PCIe reference clock sourced from AXI. */
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
......
...@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width, ...@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
*/ */
#define MR(val, ba, cmd, cs1) \ #define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *c, const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *m) const struct mx6_ddr3_cfg *ddr3_cfg)
{ {
volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1; volatile struct mmdc_p_regs *mmdc1;
u32 reg; u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
u16 CS0_END; u16 cs0_end;
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
u8 coladdr; u8 coladdr;
int clkper; /* clock period in picoseconds */ int clkper; /* clock period in picoseconds */
...@@ -215,13 +215,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, ...@@ -215,13 +215,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
clock = 400; clock = 400;
tcwl = 3; tcwl = 3;
} }
clkper = (1000*1000)/clock; /* ps */ clkper = (1000 * 1000) / clock; /* pico seconds */
todtlon = tcwl; todtlon = tcwl;
taxpd = tcwl; taxpd = tcwl;
tanpd = tcwl; tanpd = tcwl;
tcwl = tcwl;
switch (m->density) { switch (ddr3_cfg->density) {
case 1: /* 1Gb per chip */ case 1: /* 1Gb per chip */
trfc = DIV_ROUND_UP(110000, clkper) - 1; trfc = DIV_ROUND_UP(110000, clkper) - 1;
txs = DIV_ROUND_UP(120000, clkper) - 1; txs = DIV_ROUND_UP(120000, clkper) - 1;
...@@ -240,80 +239,82 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, ...@@ -240,80 +239,82 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
break; break;
default: default:
/* invalid density */ /* invalid density */
printf("invalid chip density\n"); puts("invalid chip density\n");
hang(); hang();
break; break;
} }
txpr = txs; txpr = txs;
switch (m->mem_speed) { switch (ddr3_cfg->mem_speed) {
case 800: case 800:
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
if (m->pagesz == 1) { if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(40000, clkper) - 1; tfaw = DIV_ROUND_UP(40000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
} else { } else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1; tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
} }
break; break;
case 1066: case 1066:
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
if (m->pagesz == 1) { if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(37500, clkper) - 1; tfaw = DIV_ROUND_UP(37500, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
} else { } else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1; tfaw = DIV_ROUND_UP(50000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
} }
break; break;
case 1333: case 1333:
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
if (m->pagesz == 1) { if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1; tfaw = DIV_ROUND_UP(30000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
} else { } else {
tfaw = DIV_ROUND_UP(45000, clkper) - 1; tfaw = DIV_ROUND_UP(45000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
} }
break; break;
case 1600: case 1600:
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1; tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
if (m->pagesz == 1) { if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1; tfaw = DIV_ROUND_UP(30000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
} else { } else {
tfaw = DIV_ROUND_UP(40000, clkper) - 1; tfaw = DIV_ROUND_UP(40000, clkper) - 1;
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
} }
break; break;
default: default:
printf("invalid memory speed\n"); puts("invalid memory speed\n");
hang(); hang();
break; break;
} }
txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1; txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3; tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
tcksrx = tcksre;
taonpd = DIV_ROUND_UP(2000, clkper) - 1; taonpd = DIV_ROUND_UP(2000, clkper) - 1;
tcksrx = tcksre;
taofpd = taonpd; taofpd = taonpd;
trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1; twr = DIV_ROUND_UP(15000, clkper) - 1;
tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp; trcd = trp;
trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
twr = DIV_ROUND_UP(15000, clkper) - 1;
tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
trtp = twtr; trtp = twtr;
CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127; cs0_end = 4 * sysinfo->cs_density - 1;
debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, ddr3_cfg->density);
debug("clock: %dMHz (%d ps)\n", clock, clkper); debug("clock: %dMHz (%d ps)\n", clock, clkper);
debug("memspd:%d\n", m->mem_speed); debug("memspd:%d\n", ddr3_cfg->mem_speed);
debug("tcke=%d\n", tcke); debug("tcke=%d\n", tcke);
debug("tcksrx=%d\n", tcksrx); debug("tcksrx=%d\n", tcksrx);
debug("tcksre=%d\n", tcksre); debug("tcksre=%d\n", tcksre);
...@@ -340,11 +341,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, ...@@ -340,11 +341,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
debug("twtr=%d\n", twtr); debug("twtr=%d\n", twtr);
debug("trrd=%d\n", trrd); debug("trrd=%d\n", trrd);
debug("txpr=%d\n", txpr); debug("txpr=%d\n", txpr);
debug("CS0_END=%d\n", CS0_END); debug("cs0_end=%d\n", cs0_end);
debug("ncs=%d\n", i->ncs); debug("ncs=%d\n", sysinfo->ncs);
debug("Rtt_wr=%d\n", i->rtt_wr); debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
debug("Rtt_nom=%d\n", i->rtt_nom); debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
debug("SRT=%d\n", m->SRT); debug("SRT=%d\n", ddr3_cfg->SRT);
debug("tcl=%d\n", tcl); debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr); debug("twr=%d\n", twr);
...@@ -354,142 +355,136 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, ...@@ -354,142 +355,136 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
* see: * see:
* appnote, ddr3 spreadsheet * appnote, ddr3 spreadsheet
*/ */
mmdc0->mpwldectrl0 = c->p0_mpwldectrl0; mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
mmdc0->mpwldectrl1 = c->p0_mpwldectrl1; mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
mmdc0->mpdgctrl0 = c->p0_mpdgctrl0; mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
mmdc0->mpdgctrl1 = c->p0_mpdgctrl1; mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
mmdc0->mprddlctl = c->p0_mprddlctl; mmdc0->mprddlctl = calib->p0_mprddlctl;
mmdc0->mpwrdlctl = c->p0_mpwrdlctl; mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
if (i->dsize > 1) { if (sysinfo->dsize > 1) {
mmdc1->mpwldectrl0 = c->p1_mpwldectrl0; mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
mmdc1->mpwldectrl1 = c->p1_mpwldectrl1; mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
mmdc1->mpdgctrl0 = c->p1_mpdgctrl0; mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
mmdc1->mpdgctrl1 = c->p1_mpdgctrl1; mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
mmdc1->mprddlctl = c->p1_mprddlctl; mmdc1->mprddlctl = calib->p1_mprddlctl;
mmdc1->mpwrdlctl = c->p1_mpwrdlctl; mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
} }
/* Read data DQ Byte0-3 delay */ /* Read data DQ Byte0-3 delay */
mmdc0->mprddqby0dl = (u32)0x33333333; mmdc0->mprddqby0dl = 0x33333333;
mmdc0->mprddqby1dl = (u32)0x33333333; mmdc0->mprddqby1dl = 0x33333333;
if (i->dsize > 0) { if (sysinfo->dsize > 0) {
mmdc0->mprddqby2dl = (u32)0x33333333; mmdc0->mprddqby2dl = 0x33333333;
mmdc0->mprddqby3dl = (u32)0x33333333; mmdc0->mprddqby3dl = 0x33333333;
} }
if (i->dsize > 1) {
mmdc1->mprddqby0dl = (u32)0x33333333; if (sysinfo->dsize > 1) {
mmdc1->mprddqby1dl = (u32)0x33333333; mmdc1->mprddqby0dl = 0x33333333;
mmdc1->mprddqby2dl = (u32)0x33333333; mmdc1->mprddqby1dl = 0x33333333;
mmdc1->mprddqby3dl = (u32)0x33333333; mmdc1->mprddqby2dl = 0x33333333;
mmdc1->mprddqby3dl = 0x33333333;
} }
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227; val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
mmdc0->mpodtctrl = reg; mmdc0->mpodtctrl = val;
if (i->dsize > 1) if (sysinfo->dsize > 1)
mmdc1->mpodtctrl = reg; mmdc1->mpodtctrl = val;
/* complete calibration */ /* complete calibration */
reg = (1 << 11); /* Force measurement on delay-lines */ val = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = reg; mmdc0->mpmur0 = val;
if (i->dsize > 1) if (sysinfo->dsize > 1)
mmdc1->mpmur0 = reg; mmdc1->mpmur0 = val;
/* Step 1: configuration request */ /* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */ mmdc0->mdscr = (u32)(1 << 15); /* config request */
/* Step 2: Timing configuration */ /* Step 2: Timing configuration */
reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) | mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
(tfaw << 4) | tcl; (txpdll << 9) | (tfaw << 4) | tcl;
mmdc0->mdcfg0 = reg; mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) | (tras << 16) | (1 << 15) /* trpa */ |
(1 << 15) | /* trpa */ (twr << 9) | (tmrd << 5) | tcwl;
(twr << 9) | (tmrd << 5) | tcwl; mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
mmdc0->mdcfg1 = reg; mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
mmdc0->mdcfg2 = reg; mmdc0->mdasp = cs0_end; /* CS addressing */
reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
(todtlon << 12) | (todt_idle_off << 4);
mmdc0->mdotc = reg;
mmdc0->mdasp = CS0_END; /* CS addressing */
/* Step 3: Configure DDR type */ /* Step 3: Configure DDR type */
reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) | mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
(i->mif3_mode << 9) | (i->ralat << 6); (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
mmdc0->mdmisc = reg; (sysinfo->ralat << 6);
/* Step 4: Configure delay while leaving reset */ /* Step 4: Configure delay while leaving reset */
reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0); mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
mmdc0->mdor = reg; (sysinfo->rst_to_cke << 0);
/* Step 5: Configure DDR physical parameters (density and burst len) */ /* Step 5: Configure DDR physical parameters (density and burst len) */
coladdr = m->coladdr; coladdr = ddr3_cfg->coladdr;
if (m->coladdr == 8) /* 8-bit COL is 0x3 */ if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
coladdr += 4; coladdr += 4;
else if (m->coladdr == 12) /* 12-bit COL is 0x4 */ else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
coladdr += 1; coladdr += 1;
reg = (m->rowaddr - 11) << 24 | /* ROW */ mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
(coladdr - 9) << 20 | /* COL */ (coladdr - 9) << 20 | /* COL */
(1 << 19) | /* Burst Length = 8 for DDR3 */ (1 << 19) | /* Burst Length = 8 for DDR3 */
(i->dsize << 16); /* DDR data bus size */ (sysinfo->dsize << 16); /* DDR data bus size */
mmdc0->mdctl = reg;
/* Step 6: Perform ZQ calibration */ /* Step 6: Perform ZQ calibration */
reg = (u32)0xa1390001; /* one-time HW ZQ calib */ val = 0xa1390001; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = reg; mmdc0->mpzqhwctrl = val;
if (i->dsize > 1) if (sysinfo->dsize > 1)
mmdc1->mpzqhwctrl = reg; mmdc1->mpzqhwctrl = val;
/* Step 7: Enable MMDC with desired chip select */