Commit c3259165 authored by Gabor Juhos's avatar Gabor Juhos Committed by Tom Rini
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MIPS: mips32/cache.S: save return address in t9 register

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: default avatarGabor Juhos <>
Cc: Daniel Schwierzeck <>
parent d707e5b7
......@@ -18,7 +18,7 @@
#define RA t8
#define RA t9
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
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