Commit c3259165 authored by Gabor Juhos's avatar Gabor Juhos Committed by Tom Rini
Browse files

MIPS: mips32/cache.S: save return address in t9 register



Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
parent d707e5b7
......@@ -18,7 +18,7 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
#define RA t8
#define RA t9
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
......
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