Commit c440bfe6 authored by Stefan Roese's avatar Stefan Roese
Browse files

ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board



This patch adds NAND booting support for the AMCC Acadia eval board.

Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.

I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 267 nor	;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand	;to configure the board for 267MHz NNAND booting
Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent e3cbe1f9
......@@ -75,22 +75,23 @@ LIST_8xx=" \
#########################################################################
LIST_4xx=" \
acadia ADCIOP alpr AP1000 \
AR405 ASH405 bamboo bamboo_nand \
bubinga CANBT CMS700 CPCI2DP \
CPCI405 CPCI4052 CPCI405AB CPCI405DT \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
ebony ERIC EXBITGEN G2000 \
HH405 HUB405 JSE KAREF \
katmai luan METROBOX MIP405 \
MIP405T ML2 ml300 ocotea \
OCRTC ORSG p3p440 PCI405 \
pcs440ep PIP405 PLU405 PMC405 \
PPChameleonEVB sbc405 sc3 sequoia \
sequoia_nand taishan VOH405 VOM405 \
W7OLMC W7OLMG walnut WUH405 \
XPEDITE1K yellowstone yosemite yucca \
acadia acadia_nand ADCIOP alpr \
AP1000 AR405 ASH405 bamboo \
bamboo_nand bubinga CANBT CMS700 \
CPCI2DP CPCI405 CPCI4052 CPCI405AB \
CPCI405DT CPCI440 CPCIISER4 CRAYL1 \
csb272 csb472 DASA_SIM DP405 \
DU405 ebony ERIC EXBITGEN \
G2000 HH405 HUB405 JSE \
KAREF katmai luan METROBOX \
MIP405 MIP405T ML2 ml300 \
ocotea OCRTC ORSG p3p440 \
PCI405 pcs440ep PIP405 PLU405 \
PMC405 PPChameleonEVB sbc405 sc3 \
sequoia sequoia_nand taishan VOH405 \
VOM405 W7OLMC W7OLMG walnut \
WUH405 XPEDITE1K yellowstone yosemite \
yucca \
"
#########################################################################
......
......@@ -1017,6 +1017,15 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(
acadia_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc
acadia_nand_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)nand_spl
@mkdir -p $(obj)board/amcc/acadia
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) -n $@ -a acadia ppc ppc4xx acadia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/acadia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
ADCIOP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
......
......@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cpr.o memory.o
COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
......
......@@ -63,8 +63,14 @@ int board_early_init_f(void)
acadia_gpio_init();
/* Configure 405EZ for NAND usage */
mtsdr(sdrnand0, 0x80c00000);
mtsdr(sdrultra0, 0x8d110000);
mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(sdrultra0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) |
SDR_ULTRA0_NDGPIOBP |
SDR_ULTRA0_EBCRDYEN |
SDR_ULTRA0_NFSRSTEN;
mtsdr(sdrultra0, reg);
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
......
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
static u8 boot_267_nor[] = {
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
static u8 boot_267_nand[] = {
0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 chip;
u8 *buf;
int cpu_freq;
if (argc < 3) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
cpu_freq = simple_strtol(argv[1], NULL, 10);
if (cpu_freq != 267) {
printf("Unsupported cpu-frequency - only 267 supported\n");
return 1;
}
/* use 0x50 as I2C EEPROM address for now */
chip = 0x50;
if ((strcmp(argv[2], "nor") != 0) &&
(strcmp(argv[2], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
if (strcmp(argv[2], "nand") == 0) {
switch (cpu_freq) {
case 267:
buf = boot_267_nand;
break;
default:
break;
}
} else {
switch (cpu_freq) {
case 267:
buf = boot_267_nor;
break;
default:
break;
}
}
if (i2c_write(chip, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", chip);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
printf("Error2 writing to EEPROM at address 0x%x\n", chip);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
return 0;
}
U_BOOT_CMD(
bootstrap, 3, 0, do_bootstrap,
"bootstrap - program the I2C bootstrap EEPROM\n",
"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
);
......@@ -21,6 +21,12 @@
# MA 02111-1307 USA
#
#
# AMCC 405EZ Reference Platform (Acadia) board
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFC0000
endif
......
......@@ -39,6 +39,7 @@ void sdram_init(void)
return;
}
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
......@@ -62,9 +63,12 @@ static void cram_bcr_write(u32 wr_val)
return;
}
#endif
long int initdram(int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
/* 1. EBC need to program READY, CLK, ADV for ASync mode */
......@@ -92,7 +96,12 @@ long int initdram(int board_type)
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | 0x04000000);
mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
#endif
return (CFG_MBYTES_RAM << 20);
}
......
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
common/environment.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
......@@ -155,7 +155,9 @@
* NAND U-Boot image is started from offset 0
*/
.text
#if defined(CONFIG_440)
bl reconfig_tlb0
#endif
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
......@@ -857,6 +859,38 @@ _start:
#endif /* CONFIG_405EZ */
#endif
#ifdef CONFIG_NAND_SPL
/*
* Copy SPL from cache into internal SRAM
*/
li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
mtctr r4
lis r2,CFG_NAND_BOOT_SPL_SRC@h
ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
lis r3,CFG_NAND_BOOT_SPL_DST@h
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
spl_loop:
lwzu r4,4(r2)
stwu r4,4(r3)
bdnz spl_loop
/*
* Jump to code in RAM
*/
bl 00f
00: mflr r10
lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
sub r10,r10,r3
addi r10,r10,28
mtlr r10
blr
start_ram:
sync
isync
#endif /* CONFIG_NAND_SPL */
/*----------------------------------------------------------------------- */
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
......@@ -967,12 +1001,16 @@ _start:
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
#ifdef CONFIG_NAND_SPL
bl nand_boot /* will not return */
#else
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
/* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */
......@@ -1187,23 +1225,6 @@ crit_return:
/* Cache functions.
*/
invalidate_icache:
iccci r0,r0 /* for 405, iccci invalidates the */
blr /* entire I cache */
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
dccci 0,r6 /* invalidate line */
addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
bdnz ..dcloop
blr
flush_dcache:
addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
ori r9,r9,0x8000
......@@ -1734,6 +1755,23 @@ in32:
lwz 3,0x0000(3)
blr
invalidate_icache:
iccci r0,r0 /* for 405, iccci invalidates the */
blr /* entire I cache */
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
dccci 0,r6 /* invalidate line */
addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
bdnz ..dcloop
blr
/**************************************************************************/
/* PPC405EP specific stuff */
/**************************************************************************/
......
......@@ -109,6 +109,7 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
......@@ -122,6 +123,12 @@
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define _CFG_CMD_INCLUDE (CFG_CMD_ALL)
#else
#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
#define _CFG_CMD_INCLUDE ((CFG_CMD_ALL) & ~(CFG_CMD_FLASH | CFG_CMD_IMLS))
#endif
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
......@@ -132,6 +139,63 @@
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#define CFG_NAND_ECCSIZE 256
#define CFG_NAND_ECCBYTES 3
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
#define CFG_NAND_OOBSIZE 16
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#ifdef CFG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
......@@ -209,7 +273,11 @@
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b ${fileaddr} fffc0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"upd=run load update\0" \
"nload=tftp 200000 acadia/u-boot-nand.bin\0" \
"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
"setenv filesize;saveenv\0" \
"nupd=run nload nupdate\0" \
"kozio=bootm ffc60000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
......@@ -233,24 +301,24 @@
#define CONFIG_SUPPORT_VFAT
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DTT | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_USB)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & _CFG_CMD_INCLUDE) | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DTT | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_USB)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
......@@ -312,12 +380,16 @@
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS 3