Commit c757a50b authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Hans de Goede
Browse files

ARM: sunxi: Add support for using R_UART as console



The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a console while using mmc.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarIan Campbell <ijc@hellion.org.uk>
parent 472ed064
......@@ -75,6 +75,10 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
......
......@@ -13,6 +13,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
void clock_init_uart(void)
......@@ -20,6 +21,7 @@ void clock_init_uart(void)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#if CONFIG_CONS_INDEX < 5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
......@@ -35,6 +37,10 @@ void clock_init_uart(void)
setbits_le32(&ccm->apb2_reset_cfg,
1 << (APB2_RESET_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
#else
/* enable R_PIO and R_UART clocks, and de-assert resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
......
......@@ -111,6 +111,7 @@
#define SUNXI_AVG_BASE 0x01ea0000
#define SUNXI_PRCM_BASE 0x01f01400
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUNXI_P2WI_BASE 0x01f03400
......
......@@ -172,6 +172,9 @@ enum sunxi_gpio_number {
#define SUN4I_GPI4_SDC3 2
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
......
......@@ -42,6 +42,7 @@
#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
#define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
......
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