Commit c9969947 authored by Jon Smirl's avatar Jon Smirl Committed by Wolfgang Denk
Browse files

board support patch for phyCORE-MPC5200B-tiny



Add support for the Phytec phyCORE-MPC5200B-tiny.
Code originally from Pengutronix.de.
Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on
Timer 0/1
Signed-off-by: default avatarJon Smirl <jonsmirl@gmail.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
parent 3672cd5c
......@@ -411,6 +411,10 @@ Andre Schwarz <andre.schwarz@matrix-vision.de>
mvbc_p MPC5200
mvblm7 MPC8343
Jon Smirl <jonsmirl@gmail.com>
pcm030 MPC5200
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
......
......@@ -60,6 +60,7 @@ LIST_5xxx=" \
munices \
MVBC_P \
o2dnt \
pcm030 \
pf5200 \
PM520 \
TB5200 \
......
......@@ -695,6 +695,15 @@ MVBC_P_config: unconfig
o2dnt_config: unconfig
@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
pcm030_config \
pcm030_LOWBOOT_config: unconfig
@ >include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
}
@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
pf5200_config: unconfig
@$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd
......
#
# (C) Copyright 2003-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# phyCORE-MPC5200B tiny board:
#
# Valid values for TEXT_BASE are:
#
# 0xFFF00000 boot high (standard configuration)
# 0xFF000000 boot low
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* Eric Schumann, Phytec Messtechnik
* adapted for mt46v32m16-75 DDR-RAM
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x71500F00
#define SDRAM_CONFIG1 0x73711930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2006
* Eric Schumann, Phytec Messtechnik GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm-ppc/io.h>
#include "mt46v32m16-75.h"
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
volatile struct mpc5xxx_cdm *cdm =
(struct mpc5xxx_cdm *)MPC5XXX_CDM;
volatile struct mpc5xxx_sdram *sdram =
(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
out_be32 (&sdram->ctrl,
(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
/* precharge all banks */
out_be32 (&sdram->ctrl,
(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
#ifdef SDRAM_DDR
/* set mode register: extended mode */
out_be32 (&sdram->mode, (SDRAM_EMODE));
/* set mode register: reset DLL */
out_be32 (&sdram->mode,
(SDRAM_MODE | 0x04000000));
#endif
/* precharge all banks */
out_be32 (&sdram->ctrl,
(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
/* auto refresh */
out_be32 (&sdram->ctrl,
(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
/* set mode register */
out_be32 (&sdram->mode, (SDRAM_MODE));
/* normal operation */
out_be32 (&sdram->ctrl,
(SDRAM_CONTROL | hi_addr_bit));
/* set CDM clock enable register, set MPC5200B SDRAM bus */
/* to reduced driver strength */
out_be32 (&cdm->clock_enable, (0x00CFFFFF));
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make
* real use of CONFIG_SYS_SDRAM_BASE. The code does not
* work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
phys_size_t initdram(int board_type)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
volatile struct mpc5xxx_cdm *cdm =
(struct mpc5xxx_cdm *)MPC5XXX_CDM;
volatile struct mpc5xxx_sdram *sdram =
(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
/* 256MB at 0x0 */
out_be32 (&mm->sdram0, 0x0000001b);
/* disabled */
out_be32 (&mm->sdram1, 0x10000000);
/* setup config registers */
out_be32 (&sdram->config1, SDRAM_CONFIG1);
out_be32 (&sdram->config2, SDRAM_CONFIG2);
#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
/* set tap delay */
out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
sdram_start(1);
test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else
dramsize = test2;
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
out_be32 (&mm->sdram0,
(0x13 + __builtin_ffs(dramsize >> 20) - 1));
} else {
/* disabled */
out_be32 (&mm->sdram0, 0);
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = in_be32(&mm->sdram0) & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = in_be32(&mm->sdram1) & 0xFF;
if (dramsize2 >= 0x13)
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
else
dramsize2 = 0;
#endif /* CONFIG_SYS_RAMBOOT */
return dramsize + dramsize2;
}
int checkboard(void)
{
puts("Board: phyCORE-MPC5200B-tiny\n");
return 0;
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t * bd)
{
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
#define GPIO_PSC2_4 0x02000000UL
void init_ide_reset(void)
{
volatile struct mpc5xxx_wu_gpio *wu_gpio =
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
debug("init_ide_reset\n");
/* Configure PSC2_4 as GPIO output for ATA reset */
setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
/* Deassert reset */
setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
}
void ide_set_reset(int idereset)
{
volatile struct mpc5xxx_wu_gpio *wu_gpio =
(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
debug("ide_reset(%d)\n", idereset);
if (idereset) {
clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
/* Make a delay. MPC5200 spec says 25 usec min */
udelay(500000);
} else
setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
}
#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
......@@ -45,6 +45,9 @@ int ide_preinit (void)
#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
/* ATA cs0/1 on i2c2 clk/io */
reg = (reg & ~0x03000000ul) | 0x02000000ul;
#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)
/* ATA cs0/1 on Timer 0/1 */
reg = (reg & ~0x03000000ul) | 0x03000000ul;
#else
/* ATA cs0/1 on Local Plus cs4/5 */
reg = (reg & ~0x03000000ul) | 0x01000000ul;
......
To build RAMBOOT, replace this section the main Makefile
pcm030_config \
pcm030_RAMBOOT_config \
pcm030_LOWBOOT_config: unconfig
@ >include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ echo "TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
}
@[ -z "$(findstring RAMBOOT_,$@)" ] || \
{ echo "TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
config.tmp ; \
echo "... with RAMBOOT configuration" ; \
echo "... remember to make sure that MBAR is already \
switched to 0xF0000000 !!!" ; \
}
@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
@ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
Alternative SDRAM settings:
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x715f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
/* Settings for XLB = 99 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714b0f00
#define SDRAM_CONFIG1 0x63611730
#define SDRAM_CONFIG2 0x47670000
The board ships default with the environment in EEPROM
Moving the environment to flash can be more reliable
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2006
* Eric Schumann, Phytec Messatechnik GmbH
*
* (C) Copyright 2009
* Jon Smirl <jonsmirl@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
/*-----------------------------------------------------------------------------
High Level Configuration Options
(easy to change)
-----------------------------------------------------------------------------*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
/* FEC configuration and IDE */
#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------------
Serial console configuration
-----------------------------------------------------------------------------*/
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
/*define gps port conf. */
/* register later on to */
/*enable UART function! */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
#if (TEXT_BASE == 0xFF000000) /* Boot low */
#define CONFIG_SYS_LOWBOOT 1
#endif
/* RAMBOOT will be defined automatically in memory section */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
/*-----------------------------------------------------------------------------
Autobooting
-----------------------------------------------------------------------------*/
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
/* even with bootdelay=0 */
#undef CONFIG_BOOTARGS
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
"mount root filesystem over NFS;" \
"echo"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uimage=uImage-pcm030\0" \
"oftree=oftree-pcm030.dtb\0" \
"jffs2=root-pcm030.jffs2\0" \
"uboot=u-boot-pcm030.bin\0" \
"bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
" $(mtdparts) rw\0" \
"bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
" rootfstype=jffs2\0" \
"bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
" ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
"$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
"bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
" tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
"bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
"0xfff40000\0" \
" cp.b 0x400000 0xff040000 $(filesize)\0" \
"prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
"cp.b 0x400000 0xff200000 $(filesize)\0" \
"prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
" cp.b 0x400000 0xfff40000 $(filesize)\0" \
"update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
" cp.b 0x400000 0xFFF00000 $(filesize)\0" \
"unlock=yes\0" \
""
#define CONFIG_BOOTCOMMAND "run bcmd_flash"
/*--------------------------------------------------------------------------
IPB Bus clocking configuration.
---------------------------------------------------------------------------*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*-------------------------------------------------------------------------
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
* -----------------------------------------------------------------------*/
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_XLB_PIPELINING 1
/*---------------------------------------------------------------------------
I2C configuration
---------------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*---------------------------------------------------------------------------
EEPROM CAT24WC32 configuration
---------------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
#define CONFIG_SYS_EEPROM_SIZE 2048
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
/*---------------------------------------------------------------------------
RTC configuration
---------------------------------------------------------------------------*/
#define RTC
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
/*---------------------------------------------------------------------------
Flash configuration
---------------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE 0xff000000
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
/* (= chip selects) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE