Commit cb14e93b authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/85xx: Add support for booting from NAND on MPC8572DS



Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting
from NAND.
Signed-off-by: default avatarJin Qing <b24347@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 16dad759
#
# Copyright 2007-2008 Freescale Semiconductor, Inc.
# Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
......@@ -23,4 +23,10 @@
#
# mpc8572ds board
#
ifndef NAND_SPL
ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
RESET_VECTOR_ADDRESS = 0xeffffffc
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
......@@ -85,6 +85,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4K, 1),
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_256K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
......@@ -473,6 +473,7 @@ MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freesca
MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND
MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011
P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND
P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD
......
......@@ -33,6 +33,25 @@
#define CONFIG_PHYS_64BIT
#endif
#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT
#define CONFIG_RAMBOOT_NAND
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
......@@ -41,10 +60,6 @@
#define CONFIG_MPC8572DS 1
#define CONFIG_MP 1 /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
......@@ -80,11 +95,22 @@
#define CONFIG_SYS_MEMTEST_END 0x7fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L2 Cache as L2 SRAM
*/
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE (512 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
......@@ -93,6 +119,12 @@
#endif
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
#else
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
......@@ -177,8 +209,11 @@
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
......@@ -193,7 +228,12 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
......@@ -246,6 +286,8 @@
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
......@@ -277,12 +319,22 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#else
#define CONFIG_SYS_NAND_BASE 0xfff00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
CONFIG_SYS_NAND_BASE + 0x40000, \
CONFIG_SYS_NAND_BASE + 0x80000,\
......@@ -293,6 +345,17 @@
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START \
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
......@@ -308,9 +371,17 @@
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#ifdef CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
......@@ -341,6 +412,9 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
......@@ -546,14 +620,25 @@
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024)\
+ CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
......
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# Copyright 2009-2010 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
NAND_SPL := y
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
nandobj := $(OBJTREE)/nand_spl/
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS)
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
# create symbolic links for common files
$(obj)cache.c:
@rm -f $(obj)cache.c
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
$(obj)nand_boot_fsl_elbc.c:
@rm -f $(obj)nand_boot_fsl_elbc.c
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
$(obj)nand_boot_fsl_elbc.c
$(obj)ns16550.c:
@rm -f $(obj)ns16550.c
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
endif
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
u32 sysclk_tbl[] = {
33333000, 39999600, 49999500, 66666000,
83332500, 99999000, 133332000, 166665000
};
void board_init_f(ulong bootflag)
{
int px_spd;
u32 plat_ratio, bus_clk, sys_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
/* for FPGA */
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
#else
#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
#endif
/* initialize selected port with appropriate baud rate */
px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
bus_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}
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