Commit d43e1542 authored by Tom Rini's avatar Tom Rini
Browse files
parents 980267a1 95b237ec
if ARCH_ZYNQ
config ZYNQ_CUSTOM_INIT
bool "Use custom ps7_init provided by Xilinx tool"
help
U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants.
If you want to override them with customized ones
or ps7_init code for your board is missing, please say Y here
and add ones into board/xilinx/zynq/custom_hw_platform/ directory.
choice
prompt "Xilinx Zynq board select"
optional
......@@ -14,13 +22,25 @@ config TARGET_ZYNQ_PICOZED
bool "Zynq PicoZed"
config TARGET_ZYNQ_ZC70X
bool "Zynq ZC702/ZC706 Board"
bool "Zynq ZC702/ZC706 Board (deprecated)"
select ZYNQ_CUSTOM_INIT
help
This option is deprecated. Use TARGET_ZYNQ_ZC702
or TARGET_ZYNQ_706.
config TARGET_ZYNQ_ZC702
bool "Zynq ZC702 Board"
config TARGET_ZYNQ_ZC706
bool "Zynq ZC706 Board"
config TARGET_ZYNQ_ZC770
bool "Zynq ZC770 Board"
select ZYNQ_CUSTOM_INIT
config TARGET_ZYNQ_ZYBO
bool "Zynq Zybo Board"
select ZYNQ_CUSTOM_INIT
endchoice
......@@ -37,7 +57,8 @@ config SYS_CONFIG_NAME
default "zynq_zed" if TARGET_ZYNQ_ZED
default "zynq_microzed" if TARGET_ZYNQ_MICROZED
default "zynq_picozed" if TARGET_ZYNQ_PICOZED
default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \
|| TARGET_ZYNQ_ZC70X
default "zynq_zc770" if TARGET_ZYNQ_ZC770
default "zynq_zybo" if TARGET_ZYNQ_ZYBO
......
......@@ -12,7 +12,6 @@
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
#define ZYNQ_GEM_BASEADDR0 0xE000B000
#define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
......
......@@ -85,6 +85,6 @@ __weak void ps7_init(void)
{
/*
* This function is overridden by the one in
* board/xilinx/zynq/ps7_init_gpl.c, if it exists.
* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
*/
}
......@@ -77,92 +77,11 @@ int timer_init(void)
return 0;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
ulong get_timer_masked(void)
{
ulong now;
now = readl(&timer_base->counter) /
(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
if (gd->arch.lastinc >= now) {
/* Normal mode */
gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* We have an overflow ... */
gd->arch.tbl += gd->arch.lastinc + (TIMER_LOAD_VAL /
(gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) -
now + 1;
}
gd->arch.lastinc = now;
return gd->arch.tbl;
}
void __udelay(unsigned long usec)
{
u32 countticks;
u32 timeend;
u32 timediff;
u32 timenow;
if (usec == 0)
return;
countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
1000000);
/* decrementing timer */
timeend = readl(&timer_base->counter) - countticks;
#if TIMER_LOAD_VAL != 0xFFFFFFFF
/* do not manage multiple overflow */
if (countticks >= TIMER_LOAD_VAL)
countticks = TIMER_LOAD_VAL - 1;
#endif
do {
timenow = readl(&timer_base->counter);
if (timenow >= timeend) {
/* normal case */
timediff = timenow - timeend;
} else {
if ((TIMER_LOAD_VAL - timeend + timenow) <=
countticks) {
/* overflow */
timediff = TIMER_LOAD_VAL - timeend + timenow;
} else {
/* missed the exact match */
break;
}
}
} while (timediff > 0);
}
/* Timer without interrupts */
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
return gd->arch.timer_rate_hz;
}
ps7_init_gpl.[ch]
/ps7_init_gpl.[ch]
......@@ -7,9 +7,42 @@
obj-y := board.o
# Please copy ps7_init_gpl.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
$(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o)
# Copied from Xilinx SDK 2014.4
hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform
hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform
hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform
hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform
# If you want to use customized ps7_init_gpl.c/h,
# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
# This line must be placed at the bottom of the list because
# it takes precedence over the default ones.
hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT) := custom_hw_platform
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
$(hw-platform-y)/ps7_init_gpl.o)
ifeq ($(init-objs),)
ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),)
init-objs := ps7_init_gpl.o
$(if $(CONFIG_SPL_BUILD),\
$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custome_hw_platform/))
endif
endif
obj-$(CONFIG_SPL_BUILD) += $(init-objs)
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
# To include xil_io.h
CFLAGS_ps7_init_gpl.o := -I$(srctree)/$(src)
# Warn if CONFIG_TARGET_ZYNQ_ZC70X is enabled
ifeq ($(CONFIG_TARGET_ZYNQ_ZC70X),y)
ifeq ($(CONFIG_SPL_BUILD),y)
$(warning CONFIG_TARGET_ZYNQ_ZC70X is deprecated.)
$(warning Enable CONFIG_TARGET_ZYNQ_ZC702 or CONFIG_TARGET_ZYNQ_706 instead.)
$(warning "make zynq_zc70x_defconfig" is also deprecated.)
$(warning Use "make zynq_zc702_defconfig" or "make zynq_zc706_defconfig".)
endif
endif
This diff is collapsed.
/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
*******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158731
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 50000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 100000000
#define FPGA2_FREQ 33333336
#define FPGA3_FREQ 50000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
This diff is collapsed.
/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
*******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158731
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 25000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 50000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 23809523
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 50000000
#define FPGA2_FREQ 50000000
#define FPGA3_FREQ 50000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
This diff is collapsed.
/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
*******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158731
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 25000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 50000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 50000000
#define FPGA2_FREQ 50000000
#define FPGA3_FREQ 50000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
This diff is collapsed.
/******************************************************************************
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*