Commit d5f8a6dd authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

parents ee860c60 fb536878
......@@ -43,7 +43,11 @@
/* DDR */
#define CONFIG_SYS_FSL_DDR_LE
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
......
......@@ -136,6 +136,7 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
* TODO: The kernel offers some more advanced versions of barriers, it might
* have some advantages to use them instead of the simple one here.
*/
#define mb() asm volatile("dsb sy" : : : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#define __iormb() dmb()
#define __iowmb() dmb()
......
......@@ -20,7 +20,7 @@
#include <netdev.h>
#include <fsl_esdhc.h>
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
#include <asm/immap_qe.h>
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif
......
......@@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
#include <asm/immap_qe.h>
#include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob)
{
......
......@@ -200,7 +200,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#ifdef CONFIG_SYS_FSL_CPC
#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
static void disable_cpc_sram(void)
void disable_cpc_sram(void)
{
int i;
......@@ -251,7 +251,7 @@ static void enable_tdm_law(void)
}
#endif
static void enable_cpc(void)
void enable_cpc(void)
{
int i;
u32 size = 0;
......@@ -306,6 +306,7 @@ static void invalidate_cpc(void)
#else
#define enable_cpc()
#define invalidate_cpc()
#define disable_cpc_sram()
#endif /* CONFIG_SYS_FSL_CPC */
/*
......@@ -520,7 +521,8 @@ int enable_cluster_l2(void)
u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
u32 type = in_be32(&gur->tp_ityp[idx]);
if (type & TP_ITYP_AV)
if ((type & TP_ITYP_AV) &&
TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
cluster_valid = 1;
}
......@@ -545,88 +547,15 @@ int enable_cluster_l2(void)
/*
* Initialize L2 as cache.
*
* The newer 8548, etc, parts have twice as much cache, but
* use the same bit-encoding as the older 8555, etc, parts.
*
*/
int cpu_init_r(void)
int l2cache_init(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
extern int spin_table_compat;
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 and NMG_CPU_A011 share the same workaround.
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
* fixed in 2.0. NMG_CPU_A011 is activated by default and can
* be disabled by hwconfig with syntax:
*
* fsl_cpu_a011:disable
*/
extern int enable_cpu_a011_workaround;
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
#else
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
int n, res;
n = getenv_f("hwconfig", buffer, sizeof(buffer));
if (n > 0)
buf = buffer;
res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
if (res > 0)
enable_cpu_a011_workaround = 0;
else {
if (n >= HWCONFIG_BUFFER_SIZE) {
printf("fsl_cpu_a011 was not found. hwconfig variable "
"may be too long\n");
}
enable_cpu_a011_workaround =
(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
}
#endif
if (enable_cpu_a011_workaround) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
* in write shadow mode. Checking DCWS before setting SPR 976.
*/
if (mfspr(L1CSR2) & L1CSR2_DCWS)
mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
if (spin && (*spin == 'n'))
spin_table_compat = 0;
else
spin_table_compat = 1;
#endif
puts ("L2: ");
......@@ -751,6 +680,89 @@ skip_l2:
puts("disabled\n");
#endif
return 0;
}
/*
*
* The newer 8548, etc, parts have twice as much cache, but
* use the same bit-encoding as the older 8555, etc, parts.
*
*/
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
extern int spin_table_compat;
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 and NMG_CPU_A011 share the same workaround.
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
* fixed in 2.0. NMG_CPU_A011 is activated by default and can
* be disabled by hwconfig with syntax:
*
* fsl_cpu_a011:disable
*/
extern int enable_cpu_a011_workaround;
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
#else
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
int n, res;
n = getenv_f("hwconfig", buffer, sizeof(buffer));
if (n > 0)
buf = buffer;
res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
if (res > 0) {
enable_cpu_a011_workaround = 0;
} else {
if (n >= HWCONFIG_BUFFER_SIZE) {
printf("fsl_cpu_a011 was not found. hwconfig variable "
"may be too long\n");
}
enable_cpu_a011_workaround =
(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
}
#endif
if (enable_cpu_a011_workaround) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
* in write shadow mode. Checking DCWS before setting SPR 976.
*/
if (mfspr(L1CSR2) & L1CSR2_DCWS)
mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
if (spin && (*spin == 'n'))
spin_table_compat = 0;
else
spin_table_compat = 1;
#endif
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif
......
......@@ -612,6 +612,51 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
int nodeoff;
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_PPC_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (srds_prtcl_s2) {
case 0x29:
case 0x2d:
case 0x2e:
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
switch (srds_prtcl_s4) {
case 6:
case 8:
case 14:
case 16:
#endif
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
CONFIG_SYS_ELO3_DMA3);
if (nodeoff > 0)
fdt_status_disabled(blob, nodeoff);
else
printf("WARNING: unable to disable dma3\n");
break;
default:
break;
}
}
#else
#define fdt_fixup_dma3(x)
#endif
#if defined(CONFIG_PPC_T1040)
static void fdt_fixup_l2_switch(void *blob)
{
......@@ -778,6 +823,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_usb(blob);
fdt_fixup_l2_switch(blob);
fdt_fixup_dma3(blob);
}
/*
......
......@@ -65,7 +65,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
......
......@@ -57,6 +57,12 @@ extern void unlock_ram_in_cache(void);
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
int l2cache_init(void);
void enable_cpc(void);
void disable_cpc_sram(void);
#endif
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
......
......@@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs {
#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
......@@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CONFIG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
#define CONFIG_SYS_MPC85xx_USB2_ADDR \
......
......@@ -123,6 +123,9 @@ static inline void isync(void)
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
#define mb() sync()
#define isb() isync()
/*
* Non ordered and non-swapping "raw" accessors
*/
......
......@@ -1118,7 +1118,6 @@
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
#define SVR_B4420 0x868102
......
......@@ -370,6 +370,11 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_DEEP_SLEEP
/* Jump to kernel in deep sleep case */
if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif
enable_cpc();
start_addr = in_be32(&scfg->sparecr[1]);
kernel_resume = (func_t)start_addr;
kernel_resume();
......
......@@ -203,7 +203,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap bootflash region to caching-inhibited
......@@ -214,8 +214,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for FLASH */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for FLASH */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......
......@@ -913,7 +913,7 @@ out:
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
int ret;
/*
......@@ -925,8 +925,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......
......@@ -150,7 +150,7 @@ int board_early_init_r(void)
{
#ifndef CONFIG_SYS_NO_FLASH
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
......@@ -161,8 +161,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......
......@@ -49,7 +49,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
......@@ -60,8 +60,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 1; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
......
......@@ -101,7 +101,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
......@@ -112,8 +112,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
......
......@@ -196,7 +196,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
......@@ -207,8 +207,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 1; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
......
......@@ -144,7 +144,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
......@@ -155,8 +155,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
......
......@@ -93,7 +93,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
......@@ -104,8 +104,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */