Commit d6ed3222 authored by Wolfgang Denk's avatar Wolfgang Denk Committed by Tom Rini
Browse files

Power: remove support for Freescale MPC8220



The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.

Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
parent d828a16b
......@@ -267,12 +267,6 @@ LIST_8xx="$(boards_by_cpu mpc8xx)"
LIST_4xx="$(boards_by_cpu ppc4xx)"
#########################################################################
## MPC8220 Systems
#########################################################################
LIST_8220="$(boards_by_cpu mpc8220)"
#########################################################################
## MPC824x Systems
#########################################################################
......@@ -324,7 +318,6 @@ LIST_powerpc=" \
${LIST_512x} \
${LIST_5xxx} \
${LIST_8xx} \
${LIST_8220} \
${LIST_824x} \
${LIST_8260} \
${LIST_83xx} \
......
......@@ -201,7 +201,6 @@ Directory Hierarchy:
/mpc5xx Files specific to Freescale MPC5xx CPUs
/mpc5xxx Files specific to Freescale MPC5xxx CPUs
/mpc8xx Files specific to Freescale MPC8xx CPUs
/mpc8220 Files specific to Freescale MPC8220 CPUs
/mpc824x Files specific to Freescale MPC824x CPUs
/mpc8260 Files specific to Freescale MPC8260 CPUs
/mpc85xx Files specific to Freescale MPC85xx CPUs
......
......@@ -55,8 +55,6 @@ int platform_sys_info(struct sys_info *si)
#define bi_bar bi_mbar_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
#elif defined(CONFIG_MPC8220)
#define bi_bar bi_mbar_base
#endif
#if defined(bi_bar)
......
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS = io.o fec_dma_tasks.o
COBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
interrupts.o loadtask.o speed.o \
traps.o uart.o pci.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2003-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* CPU specific code for the MPC8220 CPUs
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc8220.h>
#include <netdev.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
ulong clock = gd->cpu_clk;
char buf[32];
puts ("CPU: ");
printf (CPU_ID_STR);
printf (" (JTAG ID %08lx)", *(vu_long *) (CONFIG_SYS_MBAR + 0x50));
printf (" at %s MHz\n", strmhz (buf, clock));
return 0;
}
/* ------------------------------------------------------------------------- */
int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
volatile gptmr8220_t *gptmr = (volatile gptmr8220_t *) MMAP_GPTMR;
ulong msr;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/* Charge the watchdog timer */
gptmr->Prescl = 10;
gptmr->Count = 1;
gptmr->Mode = GPT_TMS_SGPIO;
gptmr->Control = GPT_CTRL_WDEN | GPT_CTRL_CE;
return 1;
}
/* ------------------------------------------------------------------------- */
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*
*/
unsigned long get_tbclk (void)
{
ulong tbclk;
tbclk = (gd->bus_clk + 3L) / 4L;
return (tbclk);
}
/* ------------------------------------------------------------------------- */
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_MPC8220_FEC)
mpc8220_fec_initialize(bis);
#endif
return 0;
}
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8220.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers.
*/
void cpu_init_f (void)
{
volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* Clear all port configuration */
portcfg->pcfg0 = 0;
portcfg->pcfg1 = 0;
portcfg->pcfg2 = 0;
portcfg->pcfg3 = 0;
portcfg->pcfg2 = CONFIG_SYS_GP1_PORT2_CONFIG;
portcfg->pcfg3 = CONFIG_SYS_PCI_PORT3_CONFIG | CONFIG_SYS_GP2_PORT3_CONFIG;
/*
* Flexbus Controller: configure chip selects and enable them
*/
#if defined (CONFIG_SYS_CS0_BASE)
flexbus->csar0 = CONFIG_SYS_CS0_BASE;
/* Sorcery-C can hang-up after CTRL reg initialization */
#if defined (CONFIG_SYS_CS0_CTRL)
flexbus->cscr0 = CONFIG_SYS_CS0_CTRL;
#endif
flexbus->csmr0 = ((CONFIG_SYS_CS0_MASK - 1) & 0xffff0000) | 1;
__asm__ volatile ("sync");
#endif
#if defined (CONFIG_SYS_CS1_BASE)
flexbus->csar1 = CONFIG_SYS_CS1_BASE;
flexbus->cscr1 = CONFIG_SYS_CS1_CTRL;
flexbus->csmr1 = ((CONFIG_SYS_CS1_MASK - 1) & 0xffff0000) | 1;
__asm__ volatile ("sync");
#endif
#if defined (CONFIG_SYS_CS2_BASE)
flexbus->csar2 = CONFIG_SYS_CS2_BASE;
flexbus->cscr2 = CONFIG_SYS_CS2_CTRL;
flexbus->csmr2 = ((CONFIG_SYS_CS2_MASK - 1) & 0xffff0000) | 1;
portcfg->pcfg3 |= CONFIG_SYS_CS2_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
#if defined (CONFIG_SYS_CS3_BASE)
flexbus->csar3 = CONFIG_SYS_CS3_BASE;
flexbus->cscr3 = CONFIG_SYS_CS3_CTRL;
flexbus->csmr3 = ((CONFIG_SYS_CS3_MASK - 1) & 0xffff0000) | 1;
portcfg->pcfg3 |= CONFIG_SYS_CS3_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
#if defined (CONFIG_SYS_CS4_BASE)
flexbus->csar4 = CONFIG_SYS_CS4_BASE;
flexbus->cscr4 = CONFIG_SYS_CS4_CTRL;
flexbus->csmr4 = ((CONFIG_SYS_CS4_MASK - 1) & 0xffff0000) | 1;
portcfg->pcfg3 |= CONFIG_SYS_CS4_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
#if defined (CONFIG_SYS_CS5_BASE)
flexbus->csar5 = CONFIG_SYS_CS5_BASE;
flexbus->cscr5 = CONFIG_SYS_CS5_CTRL;
flexbus->csmr5 = ((CONFIG_SYS_CS5_MASK - 1) & 0xffff0000) | 1;
portcfg->pcfg3 |= CONFIG_SYS_CS5_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
/* This section of the code cannot place in cpu_init_r(),
it will cause the system to hang */
/* enable timebase */
xlbarb->addrTenTimeOut = 0x1000;
xlbarb->dataTenTimeOut = 0x1000;
xlbarb->busActTimeOut = 0x2000;
xlbarb->config = 0x00002000;
/* Master Priority Enable */
xlbarb->mastPriority = 0;
xlbarb->mastPriEn = 0xff;
}
/*
* initialize higher level parts of CPU like time base and timers
*/
int cpu_init_r (void)
{
/* this may belongs to disable interrupt section */
/* mask all interrupts */
*(vu_long *) 0xf0000700 = 0xfffffc00;
*(vu_long *) 0xf0000714 |= 0x0001ffff;
*(vu_long *) 0xf0000710 &= ~0x00000f00;
/* route critical ints to normal ints */
*(vu_long *) 0xf0000710 |= 0x00000001;
#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
/* load FEC microcode */
loadtask (0, 2);
#endif
return (0);
}
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on code
* (C) Copyright Motorola, Inc., 2000
*
* MPC8220 dma header file
*/
#ifndef __MPC8220_DMA_H
#define __MPC8220_DMA_H
#include <common.h>
#include <mpc8220.h>
/* Task number assignment */
#define FEC_RECV_TASK_NO 0
#define FEC_XMIT_TASK_NO 1
/*---------------------------------------------------------------------
* Stuff for Ethernet Tx/Rx tasks
*---------------------------------------------------------------------
*/
/* Layout of Ethernet controller Parameter SRAM area:
* ----------------------------------------------------------------
* 0x00: TBD_BASE, base address of TX BD ring
* 0x04: TBD_NEXT, address of next TX BD to be processed
* 0x08: RBD_BASE, base address of RX BD ring
* 0x0C: RBD_NEXT, address of next RX BD to be processed
* ---------------------------------------------------------------
* ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
*/
/* base address of SRAM area to store parameters used by Ethernet tasks */
#define FEC_PARAM_BASE (MMAP_SRAM + 0x5b00)
/* base address of SRAM area for buffer descriptors */
#define FEC_BD_BASE (MMAP_SRAM + 0x5b20)
/*---------------------------------------------------------------------
* common shortcuts used by driver C code
*---------------------------------------------------------------------
*/
/* Disable SmartDMA task */
#define DMA_TASK_DISABLE(tasknum) \
{ \
volatile ushort *tcr = (ushort *)(MMAP_DMA + 0x0000001c + 2 * tasknum); \
*tcr = (*tcr) & (~0x8000); \
}
/* Enable SmartDMA task */
#define DMA_TASK_ENABLE(tasknum) \
{ \
volatile ushort *tcr = (ushort *) (MMAP_DMA + 0x0000001c + 2 * tasknum);\
*tcr = (*tcr) | 0x8000; \
}
/* Clear interrupt pending bits */
#define DMA_CLEAR_IEVENT(tasknum) \
{ \
struct mpc8220_dma *dma = (struct mpc8220_dma *)MMAP_DMA; \
dma->IntPend = (1 << tasknum); \
}
#endif /* __MPC8220_DMA_H */
This diff is collapsed.
/*
* dramSetup.h
*
* Prototypes, etc. for the Motorola MPC8220
* embedded cpu chips
*
* 2004 (c) Freescale, Inc.
* Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __INCdramsetuph
#define __INCdramsetuph
#ifndef __ASSEMBLY__
/* Where various things are in the SPD */
#define LOC_TYPE 2
#define LOC_CHECKSUM 63
#define LOC_PHYS_BANKS 5
#define LOC_LOGICAL_BANKS 17
#define LOC_ROWS 3
#define LOC_COLS 4
#define LOC_WIDTH_HIGH 7
#define LOC_WIDTH_LOW 6
#define LOC_REFRESH 12
#define LOC_BURSTS 16
#define LOC_CAS 18
#define LOC_CS 19
#define LOC_WE 20
#define LOC_Tcyc 9
#define LOC_Tac 10
#define LOC_Trp 27
#define LOC_Trrd 28
#define LOC_Trcd 29
#define LOC_Tras 30
#define LOC_Buffered 21
/* Types of memory the SPD can tell us about.
* We can actually only use SDRAM and DDR.
*/
#define TYPE_DRAM 1 /* plain old dram */
#define TYPE_EDO 2 /* EDO dram */
#define TYPE_Nibble 3 /* serial nibble memory */
#define TYPE_SDR 4 /* SDRAM */
#define TYPE_ROM 5 /* */
#define TYPE_SGRRAM 6 /* graphics memory */
#define TYPE_DDR 7 /* DDR sdram */
#define SDRAMDS_MASK 0x3 /* each field is 2 bits wide */
#define SDRAMDS_SBE_SHIFT 8 /* Clock enable drive strength */
#define SDRAMDS_SBC_SHIFT 6 /* Clocks drive strength */
#define SDRAMDS_SBA_SHIFT 4 /* Address drive strength */
#define SDRAMDS_SBS_SHIFT 2 /* SDR DQS drive strength */
#define SDRAMDS_SBD_SHIFT 0 /* Data and DQS drive strength */
#define DRIVE_STRENGTH_HIGH 0
#define DRIVE_STRENGTH_MED 1
#define DRIVE_STRENGTH_LOW 2
#define DRIVE_STRENGTH_OFF 3
#define OK 0
#define ERROR -1
/* Structure to hold information about address muxing. */
typedef struct tagMuxDescriptor {
u8 MuxValue;
u8 Columns;
u8 Rows;
u8 MoreColumns;
} muxdesc_t;
/* Structure to define one physical bank of
* memory. Note that dram size in bytes is
* (2^^(rows+columns)) * width * banks / 8
*/
typedef struct tagDramInfo {
u32 size; /* size in bytes */
u32 base; /* base address */
u8 ordinal; /* where in the memory map will we put this */
u8 type;
u8 rows;
u8 cols;
u16 width; /* width of each chip in bits */
u8 banks; /* number of chips, aka logical banks */
u8 bursts; /* bit-encoded allowable burst length */
u8 CAS; /* bit-encoded CAS latency values */
u8 CS; /* bit-encoded CS latency values */
u8 WE; /* bit-encoded WE latency values */
u8 Trp; /* bit-encoded row precharge time */
u8 Trcd; /* bit-encoded RAS to CAS delay */
u8 buffered; /* buffered or not */
u8 refresh; /* encoded refresh rate */
} draminfo_t;
#endif /* __ASSEMBLY__ */
#endif /* __INCdramsetuph */
This diff is collapsed.
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on mpc4200fec.h
* (C) Copyright Motorola, Inc., 2000
*
* odin ethernet header file
*/
#ifndef __MPC8220_FEC_H
#define __MPC8220_FEC_H
#include <common.h>
#include <mpc8220.h>
#include "dma.h"
typedef struct ethernet_register_set {
/* [10:2]addr = 00 */
/* Control and status Registers (offset 000-1FF) */
volatile u32 fec_id; /* MBAR_ETH + 0x000 */
volatile u32 ievent; /* MBAR_ETH + 0x004 */
volatile u32 imask; /* MBAR_ETH + 0x008 */
volatile u32 RES0[1]; /* MBAR_ETH + 0x00C */
volatile u32 r_des_active; /* MBAR_ETH + 0x010 */
volatile u32 x_des_active; /* MBAR_ETH + 0x014 */
volatile u32 r_des_active_cl; /* MBAR_ETH + 0x018 */
volatile u32 x_des_active_cl; /* MBAR_ETH + 0x01C */
volatile u32 ivent_set; /* MBAR_ETH + 0x020 */
volatile u32 ecntrl; /* MBAR_ETH + 0x024 */
volatile u32 RES1[6]; /* MBAR_ETH + 0x028-03C */
volatile u32 mii_data; /* MBAR_ETH + 0x040 */
volatile u32 mii_speed; /* MBAR_ETH + 0x044 */
volatile u32 mii_status; /* MBAR_ETH + 0x048 */
volatile u32 RES2[5]; /* MBAR_ETH + 0x04C-05C */
volatile u32 mib_data; /* MBAR_ETH + 0x060 */
volatile u32 mib_control; /* MBAR_ETH + 0x064 */
volatile u32 RES3[6]; /* MBAR_ETH + 0x068-7C */
volatile u32 r_activate; /* MBAR_ETH + 0x080 */
volatile u32 r_cntrl; /* MBAR_ETH + 0x084 */
volatile u32 r_hash; /* MBAR_ETH + 0x088 */
volatile u32 r_data; /* MBAR_ETH + 0x08C */
volatile u32 ar_done; /* MBAR_ETH + 0x090 */
volatile u32 r_test; /* MBAR_ETH + 0x094 */
volatile u32 r_mib; /* MBAR_ETH + 0x098 */
volatile u32 r_da_low; /* MBAR_ETH + 0x09C */
volatile u32 r_da_high; /* MBAR_ETH + 0x0A0 */
volatile u32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */
volatile u32 x_activate; /* MBAR_ETH + 0x0C0 */
volatile u32 x_cntrl; /* MBAR_ETH + 0x0C4 */
volatile u32 backoff; /* MBAR_ETH + 0x0C8 */
volatile u32 x_data; /* MBAR_ETH + 0x0CC */
volatile u32 x_status; /* MBAR_ETH + 0x0D0 */
volatile u32 x_mib; /* MBAR_ETH + 0x0D4 */
volatile u32 x_test; /* MBAR_ETH + 0x0D8 */
volatile u32 fdxfc_da1; /* MBAR_ETH + 0x0DC */
volatile u32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */
volatile u32 paddr1; /* MBAR_ETH + 0x0E4 */