Commit d7b4731e authored by Chris Packham's avatar Chris Packham Committed by Stefan Roese

arm: mvebu: Add support for NAND interface on A-38x

The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.
Signed-off-by: default avatarChris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent 46fe9eb0
...@@ -452,8 +452,15 @@ int arch_cpu_init(void) ...@@ -452,8 +452,15 @@ int arch_cpu_init(void)
u32 mvebu_get_nand_clock(void) u32 mvebu_get_nand_clock(void)
{ {
u32 reg;
if (mvebu_soc_family() == MVEBU_SOC_A38X)
reg = MVEBU_DFX_DIV_CLK_CTRL(1);
else
reg = MVEBU_CORE_DIV_CLK_CTRL(1);
return CONFIG_SYS_MVEBU_PLL_CLOCK / return CONFIG_SYS_MVEBU_PLL_CLOCK /
((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & ((readl(reg) &
NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
} }
......
...@@ -73,6 +73,7 @@ ...@@ -73,6 +73,7 @@
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8) #define MBUS_ERR_PROP_EN (1 << 8)
...@@ -92,6 +93,7 @@ ...@@ -92,6 +93,7 @@
#define SPI_PUP_EN BIT(5) #define SPI_PUP_EN BIT(5)
#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
#define NAND_ECC_DIVCKL_RATIO_OFFS 8 #define NAND_ECC_DIVCKL_RATIO_OFFS 8
#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
......
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