Commit d7c865bd authored by Curt Brune's avatar Curt Brune Committed by York Sun
Browse files

MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register

According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.

>From section of that manual:

   Source synchronous enable. This bit field must be set during
   initialization. See Section 9.6.1, "DDR SDRAM Initialization
   Sequence," details.

   0 - Reserved
   1 - The address and command are sent to the DDR SDRAMs source

In addition, Freescale application note AN2805 is also very clear that
this bit must be set.

This patch reverts a change introduced by commit


Testing Done:

and inspected the generated assembly code to verify the SS_EN bit was being
set.  There is one extra instruction emitted:

  fff9b774: 65 29 80 00  oris    r9,r9,32768

Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.

Booted an image on a MPC8541 based board successfully.
Signed-off-by: default avatarCurt Brune <>
Reviewed-by: default avatarYork Sun <>
parent b8d7652c
......@@ -1747,9 +1747,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
unsigned int clk_adjust; /* Clock adjust */
unsigned int ss_en = 0; /* Source synchronous enable */
#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* Per FSL Application Note: AN2805 */
ss_en = 1;
clk_adjust = popts->clk_adjust;
ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
ddr->ddr_sdram_clk_cntl = (0
| ((ss_en & 0x1) << 31)
| ((clk_adjust & 0xF) << 23)
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
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