Commit d873133f authored by Stefan Roese's avatar Stefan Roese Committed by Wolfgang Denk
Browse files

ppc4xx: Add Sequoia RAM-booting target



This patch adds another build target for the AMCC Sequoia PPC440EPx
eval board. This RAM-booting version is targeted for boards without
NOR FLASH (NAND booting) which need a possibility to initially
program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
configured to setup the SDRAM, this debugger can load this RAM-
booting image to the target address in SDRAM (in this case 0x1000000)
and start it there. Then U-Boot's standard NAND commands can be
used to program the NAND FLASH (e.g. "nand write ...").

Here the commands to load and start this image from the BDI2000:

440EPX>reset halt
440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
440EPX>go 0x1000000

Please note that this image automatically scans for an already
initialized SDRAM TLB (detected by EPN=0). This TLB will not be
cleared. This TLB doesn't need to be TLB #0, this RAM-booting
version will detect it and preserve it. So booting via BDI2000
will work and booting with a complete different TLB init via
U-Boot works as well.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent 837db3d8
......@@ -1533,6 +1533,17 @@ rainier_nand_config: unconfig
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sequoia_ramboot_config \
rainier_ramboot_config: unconfig
@mkdir -p $(obj)include $(obj)board/amcc/sequoia
@echo "#define CONFIG_SYS_RAMBOOT" > $(obj)include/config.h
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "LDSCRIPT = board/amcc/sequoia/u-boot-ram.lds" >> \
$(obj)board/amcc/sequoia/config.tmp
taihu_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
......
......@@ -43,12 +43,19 @@ tlbtab:
/* vxWorks needs this as first entry for the Machine Check interrupt */
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
/*
* The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
* entry is already configured for SDRAM via the JTAG debugger and mustn't
* be re-initialized by this RAM-booting U-Boot version.
*/
#ifndef CONFIG_SYS_RAMBOOT
/* TLB-entry for DDR SDRAM (Up to 2GB) */
#ifdef CONFIG_4xx_DCACHE
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
#else
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
#endif
#endif /* CONFIG_SYS_RAMBOOT */
/* TLB-entry for EBC */
tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
......
......@@ -54,7 +54,8 @@ extern void denali_core_search_data_eye(void);
************************************************************************/
phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
......
......@@ -33,7 +33,9 @@
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_SYS_NO_FLASH)
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#endif
extern void __ft_board_setup(void *blob, bd_t *bd);
ulong flash_get_size(ulong base, int banknum);
......@@ -122,16 +124,19 @@ int board_early_init_f(void)
int misc_init_r(void)
{
#if !defined(CONFIG_SYS_NO_FLASH)
uint pbcr;
int size_val = 0;
u32 reg;
#endif
#ifdef CONFIG_440EPX
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
char *act = getenv("usbact");
#endif
u32 reg;
#if !defined(CONFIG_SYS_NO_FLASH)
/* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
......@@ -171,6 +176,7 @@ int misc_init_r(void)
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
#endif /* CONFIG_SYS_NO_FLASH */
/*
* USB suff...
......@@ -515,7 +521,7 @@ int post_hotkeys_pressed(void)
}
#endif /* CONFIG_POST */
#if defined(CONFIG_NAND_U_BOOT)
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
......
/*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}
......@@ -257,6 +257,14 @@
bl board_init_f
#endif
#if defined(CONFIG_SYS_RAMBOOT)
/*
* 4xx RAM-booting U-Boot image is started from offset 0
*/
.text
bl _start_440
#endif
/*
* 440 Startup -- on reset only the top 4k of the effective
* address space is mapped in by an entry in the instruction
......@@ -444,10 +452,17 @@ skip_debug_init:
addis r0,0,0x0000
li r1,0x003f /* 64 TLB entries */
mtctr r1
rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
tlbwe r0,r1,0x0001
tlbwe r0,r1,0x0002
subi r1,r1,0x0001
li r4,0 /* Start with TLB #0 */
rsttlb:
#ifdef CONFIG_SYS_RAMBOOT
tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
#endif
tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
tlbwe r0,r4,1
tlbwe r0,r4,2
tlbnxt: addi r4,r4,1 /* Next TLB */
bdnz rsttlb
/*----------------------------------------------------------------*/
......@@ -476,7 +491,13 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
li r4,0 /* TLB # */
addi r5,r5,-4
1: lwzu r0,4(r5)
1:
#ifdef CONFIG_SYS_RAMBOOT
tlbre r3,r4,0 /* Read contents from TLB word #0 */
rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
#endif
lwzu r0,4(r5)
cmpwi r0,0
beq 2f /* 0 marks end */
lwzu r1,4(r5)
......@@ -484,7 +505,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
tlbwe r0,r4,0 /* TLB Word 0 */
tlbwe r1,r4,1 /* TLB Word 1 */
tlbwe r2,r4,2 /* TLB Word 2 */
addi r4,r4,1 /* Next TLB */
tlbnx2: addi r4,r4,1 /* Next TLB */
bdnz 1b
/*----------------------------------------------------------------*/
......
......@@ -76,6 +76,17 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_SYS_RAMBOOT)
/*
* Disable NOR FLASH commands on RAM-booting version. One main reason for this
* RAM-booting version is boards with NAND and without NOR. This image can
* be used for initial NAND programming.
*/
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#endif
/*
* Miscellaneous configurable options
*/
......
......@@ -112,13 +112,26 @@
/*
* Environment
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
#define CONFIG_ENV_SIZE (8 << 10)
/*
* In RAM-booting version, we have no environment storage. So we need to
* provide at least preliminary MAC addresses for the 4xx EMAC driver to
* register the interfaces. Those two addresses are generated via the
* tools/gen_eth_addr tool and should only be used in a closed laboratory
* environment.
*/
#define CONFIG_ETHADDR 4a:56:49:22:3e:43
#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
#endif
#if defined(CONFIG_CMD_FLASH)
/*
* FLASH related
*/
......@@ -148,6 +161,7 @@
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
#endif /* CONFIG_CMD_FLASH */
/*
* IPL (Initial Program Loader, integrated inside CPU)
......@@ -211,7 +225,8 @@
* DDR SDRAM
*/
#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
......@@ -306,7 +321,7 @@
* overwrite part of the U-Boot image which is already loaded from NAND
* to SDRAM.
*/
#if defined(CONFIG_NAND_U_BOOT)
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_POST_MEMORY_ON 0
#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
......@@ -354,7 +369,8 @@
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03017200
......
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