Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <firstname.lastname@example.org> Reviewed-by: Stephen Warren <email@example.com>
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