Commit d9ee843d authored by Wolfgang Grandegger's avatar Wolfgang Grandegger Committed by Andrew Fleming-AFLEMING
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TQM85xx: Support for Intel 82527 compatible CAN controller



This patch adds initialization of the UPMC RAM to support up to two
Intel 82527 compatible CAN controller on the TQM85xx modules.
Signed-off-by: default avatarThomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: default avatarWolfgang Grandegger <wg@grandegger.com>
parent 518d5cfe
......@@ -35,6 +35,7 @@
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff CAN 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
......@@ -49,6 +50,9 @@ struct law_entry law_table[] = {
SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
#ifdef CONFIG_CAN_DRIVER
SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC),
#endif /* CONFIG_CAN_DRIVER */
};
int num_law_entries = ARRAY_SIZE (law_table);
......@@ -95,6 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 6: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 16M PCI1 IO
* 0xe3000000 16M CAN
*/
SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
......
......@@ -31,6 +31,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <ioports.h>
#include <flash.h>
......@@ -333,6 +334,27 @@ int misc_init_r (void)
return 0;
}
#ifdef CONFIG_CAN_DRIVER
/*
* Initialize UPMC RAM
*/
static void upmc_write (u_char addr, uint val)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
out_be32 (&lbc->mdr, val);
clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
/* dummy access to perform write */
out_8 ((void __iomem *)CFG_CAN_BASE, 0);
/* normal operation */
clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
}
#endif /* CONFIG_CAN_DRIVER */
/*
* Initialize Local Bus
*/
......@@ -389,6 +411,41 @@ void local_bus_init (void)
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
#ifdef CONFIG_CAN_DRIVER
/*
* According to timing specifications EAD must be
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_hz > 83)
out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
else
out_be32 (&lbc->or2, CFG_OR2_CAN);
out_be32 (&lbc->br2, CFG_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
/* Initialize UPMC for CAN: single read */
upmc_write (0x00, 0xFFFFED00);
upmc_write (0x01, 0xCCFFCC00);
upmc_write (0x02, 0x00FFCF00);
upmc_write (0x03, 0x00FFCF00);
upmc_write (0x04, 0x00FFDC00);
upmc_write (0x05, 0x00FFCF00);
upmc_write (0x06, 0x00FFED00);
upmc_write (0x07, 0x3FFFCC07);
/* Initialize UPMC for CAN: single write */
upmc_write (0x18, 0xFFFFED00);
upmc_write (0x19, 0xCCFFEC00);
upmc_write (0x1A, 0x00FFED80);
upmc_write (0x1B, 0x00FFED80);
upmc_write (0x1C, 0x00FFFC00);
upmc_write (0x1D, 0x0FFFEC00);
upmc_write (0x1E, 0x0FFFEF00);
upmc_write (0x1F, 0x3FFFEC05);
#endif /* CONFIG_CAN_DRIVER */
}
#if defined(CONFIG_PCI)
......
......@@ -52,6 +52,8 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#undef CONFIG_CAN_DRIVER /* CAN Driver support */
/*
* sysclk for MPC85xx
*
......@@ -199,6 +201,15 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* CAN */
#ifdef CONFIG_CAN_DRIVER
#define CFG_CAN_BASE 0xE3000000 /* CAN base address */
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
#define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI)
#define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \
BR_PS_8 | BR_MS_UPMC | BR_V)
#endif /* CONFIG_CAN_DRIVER */
/*
* I2C
*/
......
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