Commit da91cfed authored by Stefan Agner's avatar Stefan Agner Committed by Tom Rini
Browse files

ARM: non-sec: flush code cacheline aligned



Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]
Signed-off-by: default avatarStefan Agner <stefan.agner@toradex.com>
Tested-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
parent 2651a052
......@@ -54,10 +54,12 @@ static void relocate_secure_section(void)
{
#ifdef CONFIG_ARMV7_SECURE_BASE
size_t sz = __secure_end - __secure_start;
unsigned long szflush = ALIGN(sz + 1, CONFIG_SYS_CACHELINE_SIZE);
memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
CONFIG_ARMV7_SECURE_BASE + sz + 1);
CONFIG_ARMV7_SECURE_BASE + szflush);
protect_secure_section();
invalidate_icache_all();
#endif
......
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