Commit db2c86d7 authored by Gabor Juhos's avatar Gabor Juhos Committed by Tom Rini
Browse files

MIPS: mips32/cache.S: use v1 register for indirect function calls



Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
parent ee8b1e29
......@@ -156,16 +156,16 @@ NESTED(mips_cache_reset, 0, ra)
*/
move a1, t2
move a2, t8
PTR_LA t7, mips_init_icache
jalr t7
PTR_LA v1, mips_init_icache
jalr v1
/*
* then initialize D-cache.
*/
move a1, t3
move a2, t8
PTR_LA t7, mips_init_dcache
jalr t7
PTR_LA v1, mips_init_dcache
jalr v1
jr RA
END(mips_cache_reset)
......
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