Commit dd9958a3 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

parents 1733259d 221fbd22
......@@ -252,39 +252,36 @@ l2_disabled:
lis r1,CONFIG_SYS_MONITOR_BASE@h
mtspr IVPR,r1
lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
addi r4,r3,CriticalInput - _start + _START_OFFSET
li r4,CriticalInput@l
mtspr IVOR0,r4 /* 0: Critical input */
addi r4,r3,MachineCheck - _start + _START_OFFSET
li r4,MachineCheck@l
mtspr IVOR1,r4 /* 1: Machine check */
addi r4,r3,DataStorage - _start + _START_OFFSET
li r4,DataStorage@l
mtspr IVOR2,r4 /* 2: Data storage */
addi r4,r3,InstStorage - _start + _START_OFFSET
li r4,InstStorage@l
mtspr IVOR3,r4 /* 3: Instruction storage */
addi r4,r3,ExtInterrupt - _start + _START_OFFSET
li r4,ExtInterrupt@l
mtspr IVOR4,r4 /* 4: External interrupt */
addi r4,r3,Alignment - _start + _START_OFFSET
li r4,Alignment@l
mtspr IVOR5,r4 /* 5: Alignment */
addi r4,r3,ProgramCheck - _start + _START_OFFSET
li r4,ProgramCheck@l
mtspr IVOR6,r4 /* 6: Program check */
addi r4,r3,FPUnavailable - _start + _START_OFFSET
li r4,FPUnavailable@l
mtspr IVOR7,r4 /* 7: floating point unavailable */
addi r4,r3,SystemCall - _start + _START_OFFSET
li r4,SystemCall@l
mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
addi r4,r3,Decrementer - _start + _START_OFFSET
li r4,Decrementer@l
mtspr IVOR10,r4 /* 10: Decrementer */
addi r4,r3,IntervalTimer - _start + _START_OFFSET
li r4,IntervalTimer@l
mtspr IVOR11,r4 /* 11: Interval timer */
addi r4,r3,WatchdogTimer - _start + _START_OFFSET
li r4,WatchdogTimer@l
mtspr IVOR12,r4 /* 12: Watchdog timer */
addi r4,r3,DataTLBError - _start + _START_OFFSET
li r4,DataTLBError@l
mtspr IVOR13,r4 /* 13: Data TLB error */
addi r4,r3,InstructionTLBError - _start + _START_OFFSET
li r4,InstructionTLBError@l
mtspr IVOR14,r4 /* 14: Instruction TLB error */
addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
li r4,DebugBreakpoint@l
mtspr IVOR15,r4 /* 15: Debug */
#endif
......@@ -1121,7 +1118,7 @@ switch_as:
/*--------------------------------------------------------------*/
lis r3,CONFIG_SYS_MONITOR_BASE@h
ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
addi r3,r3,_start_cont - _start + _START_OFFSET
addi r3,r3,_start_cont - _start
mtlr r3
blr
#endif
......@@ -1165,7 +1162,6 @@ _start_cont:
/* NOTREACHED - board_init_f() does not return */
#ifndef MINIMAL_SPL
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
......@@ -1185,7 +1181,6 @@ _start_of_vectors:
STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
/* Alignment exception. */
. = 0x0600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
......@@ -1193,87 +1188,20 @@ Alignment:
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x0700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
/* No FPU on MPC85xx. This exception is not supposed to happen.
*/
STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
. = 0x0900
/*
* r0 - SYSCALL number
* r3-... arguments
*/
SystemCall:
addis r11,r0,0 /* get functions table addr */
ori r11,r11,0 /* Note: this code is patched in trap_init */
addis r12,r0,0 /* get number of functions */
ori r12,r12,0
cmplw 0,r0,r12
bge 1f
rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
add r11,r11,r0
lwz r11,0(r11)
li r20,0xd00-4 /* Get stack pointer */
lwz r12,0(r20)
subi r12,r12,12 /* Adjust stack pointer */
li r0,0xc00+_end_back-SystemCall
cmplw 0,r0,r12 /* Check stack overflow */
bgt 1f
stw r12,0(r20)
mflr r0
stw r0,0(r12)
mfspr r0,SRR0
stw r0,4(r12)
mfspr r0,SRR1
stw r0,8(r12)
li r12,0xc00+_back-SystemCall
mtlr r12
mtspr SRR0,r11
1: SYNC
rfi
_back:
mfmsr r11 /* Disable interrupts */
li r12,0
ori r12,r12,MSR_EE
andc r11,r11,r12
SYNC /* Some chip revs need this... */
mtmsr r11
SYNC
li r12,0xd00-4 /* restore regs */
lwz r12,0(r12)
lwz r11,0(r12)
mtlr r11
lwz r11,4(r12)
mtspr SRR0,r11
lwz r11,8(r12)
mtspr SRR1,r11
addi r12,r12,12 /* Adjust stack pointer */
li r20,0xd00-4
stw r12,0(r20)
SYNC
rfi
_end_back:
STD_EXCEPTION(0x0900, SystemCall, UnknownException)
STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
......@@ -1293,32 +1221,22 @@ _end_of_vectors:
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
* r23 is the address of the handler.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
mtspr SPRG2,r22 /* r1 is now kernel sp */
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
mtctr r23 /* virtual address of handler */
mtmsr r20
bctrl
int_return:
mfmsr r28 /* Disable interrupts */
......@@ -1350,66 +1268,6 @@ int_return:
SYNC
rfi
crit_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SPRN_CSRR0,r2
mtspr SPRN_CSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfci
mck_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SPRN_MCSRR0,r2
mtspr SPRN_MCSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfmci
/* Cache functions.
*/
.globl flush_icache
......@@ -1494,11 +1352,6 @@ dcache_status:
andi. r3,r3,L1CSR0_DCE
blr
.globl get_pir
get_pir:
mfspr r3,PIR
blr
.globl get_pvr
get_pvr:
mfspr r3,PVR
......@@ -1509,11 +1362,6 @@ get_svr:
mfspr r3,SVR
blr
.globl wr_tcr
wr_tcr:
mtspr TCR,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
......@@ -1728,7 +1576,7 @@ relocate_code:
* initialization, now running from RAM.
*/
addi r0,r10,in_ram - _start + _START_OFFSET
addi r0,r10,in_ram - _start
/*
* As IVPR is going to point RAM address,
......@@ -1816,89 +1664,41 @@ clear_bss:
*/
.globl trap_init
trap_init:
mflr r4 /* save link register */
GET_GOT
lwz r7,GOT(_start_of_vectors)
lwz r8,GOT(_end_of_vectors)
li r9,0x100 /* reset vector always at 0x100 */
cmplw 0,r7,r8
bgelr /* return if r7>=r8 - just in case */
1:
lwz r0,0(r7)
stw r0,0(r9)
addi r7,r7,4
addi r9,r9,4
cmplw 0,r7,r8
bne 1b
/* Update IVORs as per relocation */
mtspr IVPR,r3
/*
* relocate `hdlr' and `int_return' entries
*/
li r7,.L_CriticalInput - _start + _START_OFFSET
bl trap_reloc
li r7,.L_MachineCheck - _start + _START_OFFSET
bl trap_reloc
li r7,.L_DataStorage - _start + _START_OFFSET
bl trap_reloc
li r7,.L_InstStorage - _start + _START_OFFSET
bl trap_reloc
li r7,.L_ExtInterrupt - _start + _START_OFFSET
bl trap_reloc
li r7,.L_Alignment - _start + _START_OFFSET
bl trap_reloc
li r7,.L_ProgramCheck - _start + _START_OFFSET
bl trap_reloc
li r7,.L_FPUnavailable - _start + _START_OFFSET
bl trap_reloc
li r7,.L_Decrementer - _start + _START_OFFSET
bl trap_reloc
li r7,.L_IntervalTimer - _start + _START_OFFSET
li r8,_end_of_vectors - _start + _START_OFFSET
2:
bl trap_reloc
addi r7,r7,0x100 /* next exception vector */
cmplw 0,r7,r8
blt 2b
/* Update IVORs as per relocated vector table address */
li r7,0x0100
mtspr IVOR0,r7 /* 0: Critical input */
li r7,0x0200
mtspr IVOR1,r7 /* 1: Machine check */
li r7,0x0300
mtspr IVOR2,r7 /* 2: Data storage */
li r7,0x0400
mtspr IVOR3,r7 /* 3: Instruction storage */
li r7,0x0500
mtspr IVOR4,r7 /* 4: External interrupt */
li r7,0x0600
mtspr IVOR5,r7 /* 5: Alignment */
li r7,0x0700
mtspr IVOR6,r7 /* 6: Program check */
li r7,0x0800
mtspr IVOR7,r7 /* 7: floating point unavailable */
li r7,0x0900
mtspr IVOR8,r7 /* 8: System call */
li r4,CriticalInput@l
mtspr IVOR0,r4 /* 0: Critical input */
li r4,MachineCheck@l
mtspr IVOR1,r4 /* 1: Machine check */
li r4,DataStorage@l
mtspr IVOR2,r4 /* 2: Data storage */
li r4,InstStorage@l
mtspr IVOR3,r4 /* 3: Instruction storage */
li r4,ExtInterrupt@l
mtspr IVOR4,r4 /* 4: External interrupt */
li r4,Alignment@l
mtspr IVOR5,r4 /* 5: Alignment */
li r4,ProgramCheck@l
mtspr IVOR6,r4 /* 6: Program check */
li r4,FPUnavailable@l
mtspr IVOR7,r4 /* 7: floating point unavailable */
li r4,SystemCall@l
mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
li r7,0x0a00
mtspr IVOR10,r7 /* 10: Decrementer */
li r7,0x0b00
mtspr IVOR11,r7 /* 11: Interval timer */
li r7,0x0c00
mtspr IVOR12,r7 /* 12: Watchdog timer */
li r7,0x0d00
mtspr IVOR13,r7 /* 13: Data TLB error */
li r7,0x0e00
mtspr IVOR14,r7 /* 14: Instruction TLB error */
li r7,0x0f00
mtspr IVOR15,r7 /* 15: Debug */
lis r7,0x0
mtspr IVPR,r7
mtlr r4 /* restore link register */
li r4,Decrementer@l
mtspr IVOR10,r4 /* 10: Decrementer */
li r4,IntervalTimer@l
mtspr IVOR11,r4 /* 11: Interval timer */
li r4,WatchdogTimer@l
mtspr IVOR12,r4 /* 12: Watchdog timer */
li r4,DataTLBError@l
mtspr IVOR13,r4 /* 13: Data TLB error */
li r4,InstructionTLBError@l
mtspr IVOR14,r4 /* 14: Instruction TLB error */
li r4,DebugBreakpoint@l
mtspr IVOR15,r4 /* 15: Debug */
blr
.globl unlock_ram_in_cache
......
......@@ -45,7 +45,7 @@ static inline bool has_erratum_a007186(void)
return IS_SVR_REV(svr, 2, 0);
case SVR_T2081:
case SVR_T2080:
return IS_SVR_REV(svr, 1, 0);
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
}
return false;
......
......@@ -32,12 +32,12 @@ static const struct board_specific_parameters udimm0[] = {
{2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
{2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
{2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
{1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
{1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
{1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
{}
};
......
......@@ -19,6 +19,7 @@
#include <fm_eth.h>
#include "t208xrdb.h"
#include "cpld.h"
#include "../common/vid.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -85,6 +86,12 @@ int board_early_init_r(void)
setup_portals();
#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
return 0;
}
......
......@@ -1747,9 +1747,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
unsigned int clk_adjust; /* Clock adjust */
unsigned int ss_en = 0; /* Source synchronous enable */
#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* Per FSL Application Note: AN2805 */
ss_en = 1;
#endif
clk_adjust = popts->clk_adjust;
ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
ddr->ddr_sdram_clk_cntl = (0
| ((ss_en & 0x1) << 31)
| ((clk_adjust & 0xF) << 23)
);
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}
......
......@@ -482,7 +482,6 @@ int testdram(void);
defined(CONFIG_8xx)
uint get_immr (uint);
#endif
uint get_pir (void);
#if defined(CONFIG_MPC5xxx)
uint get_svr (void);
#endif
......
......@@ -255,7 +255,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
......@@ -602,7 +602,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
......
......@@ -140,6 +140,11 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
......@@ -448,6 +453,17 @@ unsigned long get_board_ddr_clk(void);
#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
#define CONFIG_VOL_MONITOR_IR36021_SET
#define CONFIG_VOL_MONITOR_IR36021_READ
/* The lowest and highest voltage allowed for T208xRDB */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
/*
* RapidIO
......@@ -646,8 +662,8 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHY_CORTINA
#define CONFIG_PHY_AQ1202
#define CONFIG_PHY_REALTEK
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
......
......@@ -638,6 +638,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_CORTINA
#define CONFIG_SYS_CORTINA_FW_IN_NOR
#define CONFIG_CORTINA_FW_ADDR 0xefe00000
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define CONFIG_PHY_TERANETICS
......
......@@ -50,8 +50,14 @@
/* Physical address should be a function call */
#ifndef __ASSEMBLY__
extern unsigned long long get_phys_ccsrbar_addr_early(void);
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#endif
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#define CONFIG_PHYS_64BIT
/* Virtual address range for PCI region maps */
#define CONFIG_SYS_PCI_MAP_START 0x80000000
......
......@@ -6,10 +6,6 @@
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
/* define for common ppc_asm.tmpl */
#define EXC_OFF_SYS_RESET 0x100 /* System reset */
#define _START_OFFSET 0
#if defined(CONFIG_E500)
#include <e500.h>
#endif
......