Commit de09c43b authored by Peng Fan's avatar Peng Fan Committed by Stefano Babic

imx: imx-common: introduce Resource Domain Controller support

Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: default avatarYe.Li <ye.li@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
parent 613e0106
......@@ -3,3 +3,11 @@ config IMX_CONFIG
config ROM_UNIFIED_SECTIONS
bool
config IMX_RDC
bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7
help
i.MX Resource domain controller is used to assign masters
and peripherals to differet domains. This can be used to
isolate resources.
......@@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))
......
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm-generic/errno.h>
/*
* Check if the RDC Semaphore is required for this peripheral.
*/
static inline int imx_rdc_check_sema_required(int per_id)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 reg;
reg = readl(&imx_rdc->pdap[per_id]);
/*
* No semaphore:
* Intial value or this peripheral is assigned to only one domain
*/
if (!(reg & RDC_PDAP_SREQ_MASK))
return -ENOENT;
return 0;
}
/*
* Check the peripheral read / write access permission on Domain [dom_id].
*/
int imx_rdc_check_permission(int per_id, int dom_id)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 reg;
reg = readl(&imx_rdc->pdap[per_id]);
if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
return -EACCES; /*No access*/
return 0;
}
/*
* Lock up the RDC semaphore for this peripheral if semaphore is required.
*/
int imx_rdc_sema_lock(int per_id)
{
struct rdc_sema_regs *imx_rdc_sema;
int ret;
u8 reg;
ret = imx_rdc_check_sema_required(per_id);
if (ret)
return ret;
if (per_id < SEMA_GATES_NUM)
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
else
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
do {
writeb(RDC_SEMA_PROC_ID,
&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
break; /* Get the Semaphore*/
} while (1);
return 0;
}
/*
* Unlock the RDC semaphore for this peripheral if main CPU is the
* semaphore owner.
*/
int imx_rdc_sema_unlock(int per_id)
{
struct rdc_sema_regs *imx_rdc_sema;
int ret;
u8 reg;
ret = imx_rdc_check_sema_required(per_id);
if (ret)
return ret;
if (per_id < SEMA_GATES_NUM)
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
else
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
return 1; /*Not the semaphore owner */
writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
return 0;
}
/*
* Setup RDC setting for one peripheral
*/
int imx_rdc_setup_peri(rdc_peri_cfg_t p)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 reg = 0;
u32 share_count = 0;
u32 peri_id = p & RDC_PERI_MASK;
u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
/* No domain assigned */
if (domain == 0)
return -EINVAL;
reg |= domain;
share_count = (domain & 0x3)
+ ((domain >> 2) & 0x3)
+ ((domain >> 4) & 0x3)
+ ((domain >> 6) & 0x3);
if (share_count > 0x3)
reg |= RDC_PDAP_SREQ_MASK;
writel(reg, &imx_rdc->pdap[peri_id]);
return 0;
}
/*
* Setup RDC settings for multiple peripherals
*/
int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
unsigned count)
{
rdc_peri_cfg_t const *p = peripherals_list;
int i, ret;
for (i = 0; i < count; i++) {
ret = imx_rdc_setup_peri(*p);
if (ret)
return ret;
p++;
}
return 0;
}
/*
* Setup RDC setting for one master
*/
int imx_rdc_setup_ma(rdc_ma_cfg_t p)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
return 0;
}
/*
* Setup RDC settings for multiple masters
*/
int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
{
rdc_ma_cfg_t const *p = masters_list;
int i, ret;
for (i = 0; i < count; i++) {
ret = imx_rdc_setup_ma(*p);
if (ret)
return ret;
p++;
}
return 0;
}
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_RDC_H__
#define __IMX_RDC_H__
#error "Please select cpu"
#endif /* __IMX_RDC_H__*/
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __RDC_SEMA_H__
#define __RDC_SEMA_H__
/*
* rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
*
* [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
* d3 d2 d1 d0 | master id | peri id
* d[x] means domain[x], x can be [3 - 0].
*/
typedef u32 rdc_peri_cfg_t;
typedef u32 rdc_ma_cfg_t;
#define RDC_PERI_SHIFT 0
#define RDC_PERI_MASK 0xFF
#define RDC_DOMAIN_SHIFT_BASE 16
#define RDC_DOMAIN_MASK 0xFF0000
#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
#define RDC_MASTER_SHIFT 8
#define RDC_MASTER_MASK 0xFF00
#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
(domain_id << RDC_DOMAIN_SHIFT_BASE))
/* The Following macro definitions are common to i.MX6SX and i.MX7D */
#define SEMA_GATES_NUM 64
#define RDC_MDA_DID_SHIFT 0
#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
#define RDC_MDA_LCK_SHIFT 31
#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
RDC_PDAP_DR_MASK(domain))
#define RDC_PDAP_SREQ_SHIFT 30
#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
#define RDC_PDAP_LCK_SHIFT 31
#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
#define RDC_MRSA_SADR_SHIFT 7
#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
#define RDC_MREA_EADR_SHIFT 7
#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
#define RDC_MRC_DW_SHIFT(domain) (domain)
#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
RDC_MRC_DR_MASK(domain))
#define RDC_MRC_ENA_SHIFT 30
#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
#define RDC_MRC_LCK_SHIFT 31
#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
#define RDC_MRVS_VDID_SHIFT 0
#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
#define RDC_MRVS_AD_SHIFT 4
#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
#define RDC_MRVS_VADDR_SHIFT 5
#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
#define RDC_SEMA_GATE_GTFSM_SHIFT 0
#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
#define RDC_SEMA_GATE_LDOM_SHIFT 5
#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
int imx_rdc_check_permission(int per_id, int dom_id);
int imx_rdc_sema_lock(int per_id);
int imx_rdc_sema_unlock(int per_id);
int imx_rdc_setup_peri(rdc_peri_cfg_t p);
int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
unsigned count);
int imx_rdc_setup_ma(rdc_ma_cfg_t p);
int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
#endif /* __RDC_SEMA_H__*/
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