Commit de1d0a69 authored by Jon Loeliger's avatar Jon Loeliger
Browse files

Fix style issues primarily in 85xx and 83xx boards.

    - C++ comments
    - Trailing white space
    - Indentation not by TAB
    - Excessive amount of empty lines
    - Trailing empty lines
parent b0e32949
======================================================================
Changes for U-Boot 1.1.3:
======================================================================
* Patch by Jon Loeliger
Fix style issues primarily in 85xx and 83xx boards.
- C++ comments
- Trailing white space
- Indentation not by TAB
- Excessive amount of empty lines
- Trailing empty lines
* Patch by Ron Alder, 11 July 2005
Add Xianghua Xiao and Lunsheng Wang's support for the
GDA MPC8540 EVAL board.
......
......@@ -53,7 +53,6 @@ int board_early_init_f (void)
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
long int initdram (int board_type)
{
volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
......@@ -148,7 +147,7 @@ int checkboard (void)
return 0;
}
#if defined(CONFIG_PCI) //copy from mpc85xx
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found
*/
......@@ -190,8 +189,8 @@ pci_init_board(void)
}
/*
if MPC8349ADS is soldered with SDRAM
*/
* if MPC8349ADS is soldered with SDRAM
*/
#if defined(CFG_BR2_PRELIM) \
&& defined(CFG_OR2_PRELIM) \
&& defined(CFG_LBLAWBAR2_PRELIM) \
......@@ -207,7 +206,6 @@ sdram_init(void)
volatile lbus8349_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
......@@ -233,32 +231,33 @@ sdram_init(void)
lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
asm("sync");
/*1 times*/
/*1 times*/
*sdram_addr = 0xff;
udelay(100);
/*2 times*/
/*2 times*/
*sdram_addr = 0xff;
udelay(100);
/*3 times*/
/*3 times*/
*sdram_addr = 0xff;
udelay(100);
/*4 times*/
/*4 times*/
*sdram_addr = 0xff;
udelay(100);
/*5 times*/
/*5 times*/
*sdram_addr = 0xff;
udelay(100);
/*6 times*/
/*6 times*/
*sdram_addr = 0xff;
udelay(100);
/*7 times*/
/*7 times*/
*sdram_addr = 0xff;
udelay(100);
/*8 times*/
/*8 times*/
*sdram_addr = 0xff;
udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation*/
/* 0x58636733;mode register write operation */
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
......@@ -275,4 +274,3 @@ sdram_init(void)
put("SDRAM on Local Bus is NOT available!\n");
}
#endif
......@@ -23,34 +23,15 @@
* MA 02111-1307 USA
*/
extern long int spd_sdram (void);
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
extern long int spd_sdram (void);
long int fixed_sdram (void);
/* MPC8540ADS Board Status & Control Registers */
#if 0
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
#endif
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
......@@ -74,7 +55,8 @@ int checkboard (void)
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
printf ("\tLBC: %lu MHz\n",
sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
} else {
printf("\tLBC: unknown\n");
}
......@@ -199,7 +181,6 @@ long int initdram (int board_type)
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
......@@ -234,14 +215,13 @@ int testdram (void)
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
......@@ -251,21 +231,21 @@ long int fixed_sdram (void)
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
#if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000;
#endif
#endif
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else
#else
ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif
#endif
asm("sync; isync; msync");
udelay(500);
#endif
#endif
return (CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
......@@ -101,7 +101,7 @@ abbrev_spec (char *str, flash_info_t ** pinfo, int *psf, int *psl)
* erase and protect commands. The range of the addresses on which
* either of the commands is to operate can be given in two forms:
* 1. <cmd> start end - operate on <'start', 'end')
* 2. <cmd> start +length - operate on <'start', start + length)
* 2. <cmd> start +length - operate on <'start', start + length)
* If the second form is used and the end address doesn't fall on the
* sector boundary, than it will be adjusted to the next sector boundary.
* If it isn't in the flash, the function will fail (return -1).
......
......@@ -455,9 +455,8 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
i = usb_init();
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
if (i >= 0)
if (i >= 0)
usb_stor_curr_dev = usb_stor_scan(1);
#endif
return 0;
}
......
......@@ -47,7 +47,7 @@
#endif
#undef USB_DEBUG
#undef USB_DEBUG
#ifdef USB_DEBUG
#define USB_PRINTF(fmt,args...) printf (fmt ,##args)
......@@ -342,7 +342,7 @@ int usb_clear_halt(struct usb_device *dev, int pipe)
if (result < 0)
return result;
/*
/*
* NOTE: we do not get status and verify reset was successful
* as some devices are reported to lock up upon this check..
*/
......@@ -517,13 +517,12 @@ int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char
/* some devices are flaky */
result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
(USB_DT_STRING << 8) + index, langid, buf, size,
(USB_DT_STRING << 8) + index, langid, buf, size,
USB_CNTL_TIMEOUT);
if (result > 0)
break;
}
}
return result;
}
......@@ -572,7 +571,7 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid,
}
if (rc < 2)
rc = -1;
rc = -1;
return rc;
}
......@@ -721,10 +720,9 @@ int usb_new_device(struct usb_device *dev)
}
}
dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0;
/* find the port number we're at */
if (parent) {
for (j = 0; j < parent->maxchild; j++) {
if (parent->children[j] == dev) {
port = j;
......@@ -958,7 +956,6 @@ static int hub_port_reset(struct usb_device *dev, int port,
return -1;
if (portstatus & USB_PORT_STAT_ENABLE) {
break;
}
......
......@@ -229,7 +229,7 @@ int usb_stor_scan(int mode)
}
if(usb_storage_probe(dev,0,&usb_stor[usb_max_devs])) { /* ok, it is a storage devices */
/* get info and fill it in */
if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs]))
if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs]))
usb_max_devs++;
} /* if storage device */
if(usb_max_devs==USB_MAX_STOR_DEV) {
......@@ -237,7 +237,7 @@ int usb_stor_scan(int mode)
break;
}
} /* for */
usb_disable_asynch(0); /* asynch transfer allowed */
printf("%d Storage Device(s) found\n", usb_max_devs);
if(usb_max_devs>0)
......@@ -656,7 +656,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
retry = 0;
again:
USB_STOR_PRINTF("STATUS phase\n");
result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE,
result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE,
&actlen, USB_CNTL_TIMEOUT*5);
/* special handling of STALL in STATUS phase */
......@@ -1134,7 +1134,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
dev->descriptor.idProduct == 0x2010)
)
USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n");
else
else
ss->transport_reset(ss);
pccb->pdata = usb_stor_buf;
......@@ -1145,7 +1145,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
if(usb_inquiry(pccb,ss))
return -1;
perq = usb_stor_buf[0];
modi = usb_stor_buf[1];
if((perq & 0x1f) == 0x1f) {
......
......@@ -53,7 +53,6 @@
#define OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
/* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
......@@ -1221,7 +1220,6 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
}
/*-------------------------------------------------------------------------*/
/* common code for handling submit messages - used for all but root hub */
......@@ -1294,7 +1292,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
wait_ms(1);
if (!urb_finished)
dbg("\%");
} else {
err("CTL:TIMEOUT ");
dbg("submit_common_msg: TO status %x\n", stat);
......@@ -1511,7 +1509,7 @@ hc_interrupt (void)
ohci->disabled++;
err ("%s device removed!", ohci->slot_name);
return -1;
} else if ((ints &= readl (&regs->intrenable)) == 0) {
dbg("hc_interrupt: returning..\n");
return 0xff;
......
......@@ -1261,7 +1261,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
stat = USB_ST_CRC_ERR;
break;
}
/* NOTE: since we are not interrupt driven in U-Boot and always
* handle only one URB at a time, we cannot assume the
* transaction finished on the first successful return from
......@@ -1483,7 +1483,7 @@ hc_interrupt (void)
struct ohci_regs *regs = ohci->regs;
int ints;
int stat = -1;
if ((ohci->hcca->done_head != 0) &&
!(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
......@@ -1493,7 +1493,7 @@ hc_interrupt (void)
ohci->disabled++;
err ("%s device removed!", ohci->slot_name);
return -1;
} else if ((ints &= readl (&regs->intrenable)) == 0) {
dbg("hc_interrupt: returning..\n");
return 0xff;
......
......@@ -161,4 +161,3 @@ int cpu_init_r (void)
{
return 0;
}
......@@ -45,12 +45,12 @@ void
pci_mpc83xx_init(volatile struct pci_controller *hose)
{
volatile immap_t * immr;
volatile clk8349_t * clk;
volatile clk8349_t * clk;
volatile law8349_t * pci_law;
volatile pot8349_t * pci_pot;
volatile pcictrl8349_t * pci_ctrl;
volatile pciconf8349_t * pci_conf;
u8 val8,tmp8,ret;
u16 reg16,tmp16;
u32 val32,tmp32;
......@@ -69,7 +69,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
udelay(2000);
clk->occr = 0xff000000;
udelay(2000);
/*
* Configure PCI Local Access Windows
*/
......@@ -89,7 +89,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
//#if defined(CONFIG_PCI_2)
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
......@@ -98,8 +98,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
//#endif
/*
* Configure PCI Inbound Translation Windows
*/
......@@ -131,13 +130,13 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
val8 = 0x34;
ret = i2c_write(0x26,0x7,1,&val8,1);
#if defined(PCI_64BIT)
val8 = 0xf4; // PMC2<->PCI1 64bit
val8 = 0xf4; /* PMC2<->PCI1 64bit */
#elif defined(PCI_ALL_PCI1)
val8 = 0xf3; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit
val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
#elif defined(PCI_ONE_PCI1)
val8 = 0xf9; // PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit
val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
#elif defined(PCI_TWO_PCI1)
val8 = 0xf5; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit
val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
#else
val8 = 0xf5;
#endif
......@@ -160,7 +159,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_ctrl[0].gcr = 1;
#ifndef PCI_64BIT
pci_ctrl[1].gcr = 1;
#endif
#endif
udelay(2000);
hose[0].first_busno = 0;
......@@ -186,7 +185,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
#define PCI_CLASS_BRIDGE 0x06
reg16 = 0xff;
tmp32 = 0xffff;
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
......@@ -219,7 +218,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
(CFG_IMMRBAR+0x8380),
(CFG_IMMRBAR+0x8384));
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
......
......@@ -2,5 +2,5 @@
#ifndef FIXME
#if 0
b _start_e500
#endif
#endif
#endif
......@@ -36,20 +36,16 @@
#ifdef CONFIG_SPD_EEPROM
#if defined(CONFIG_DDR_ECC)
extern void dma_init(void);
extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
#endif
#ifndef CFG_READ_SPD
#define CFG_READ_SPD i2c_read
#endif
/*
* Convert picoseconds into clock cycles (rounding up if needed).
*/
......@@ -67,14 +63,12 @@ picos_to_clk(int picos)
return clks;
}
unsigned int
banksize(unsigned char row_dens)
{
return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
}
long int spd_sdram(int(read_spd)(uint addr))
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
......@@ -86,8 +80,8 @@ long int spd_sdram(int(read_spd)(uint addr))
unsigned int law_size;
unsigned char caslat;
unsigned int trfc, trfc_clk, trfc_low;
#warning Current spd_sdram does not fit its usage... adjust implementation or API...
#warning Current spd_sdram does not fit its usage... adjust implementation or API...
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
......@@ -111,7 +105,7 @@ long int spd_sdram(int(read_spd)(uint addr))
debug("\n");
debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
if (spd.nrows == 2) {
ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
| ((banksize(spd.row_dens) >> 23) - 1) );
......@@ -298,9 +292,12 @@ long int spd_sdram(int(read_spd)(uint addr))
udelay(500);
ddr->sdram_clk_cntl = 0x82000000;/*SS_EN=1, CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after address/command*/
/*
* SS_EN=1,
* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
* clock cycle after address/command
*/
ddr->sdram_clk_cntl = 0x82000000;
/*
* Figure out the settings for the sdram_cfg register. Build up
......@@ -339,7 +336,6 @@ long int spd_sdram(int(read_spd)(uint addr))
#endif
ddr->sdram_cfg = tmp;
asm("sync;isync");
udelay(500);
......@@ -347,7 +343,6 @@ long int spd_sdram(int(read_spd)(uint addr))
return memsize;/*in MBytes*/
}
#endif /* CONFIG_SPD_EEPROM */
......@@ -407,7 +402,7 @@ ddr_enable_ecc(unsigned int dram_size)
*/
ddr->err_disable = 0x00000000;
asm("sync;isync");
#endif
#endif
}
#endif /* CONFIG_DDR_ECC */
......@@ -101,7 +101,7 @@ int get_clocks (void)
u32 corecnf_tab_index;
u8 corepll;
u32 lcrr;
u32 csb_clk;
u32 tsec1_clk;
u32 tsec2_clk;
......@@ -113,10 +113,10 @@ int get_clocks (void)
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
#ifndef CFG_HRCW_HIGH
# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
#endif /* CFG_HCWD_HIGH */
......@@ -133,7 +133,6 @@ int get_clocks (void)
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
/* FIXME: findout if there is a way to issue some warning */
return -2;
}
if (im->clk.spmr & SPMR_CKID) {
pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
......@@ -157,17 +156,16 @@ int get_clocks (void)
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */
spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
}
else {
csb_clk = pci_sync_in * spmf * (1 + clkin_div);
}
sccr = im->clk.sccr;
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
......@@ -186,7 +184,7 @@ int get_clocks (void)
/* unkown SCCR_TSEC1CM value */
return -4;
}
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
......@@ -205,7 +203,7 @@ int get_clocks (void)
return -5;
}
i2c_clk = tsec2_clk;
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {