Commit dee332ff authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

parents 1739564e e7eb277d
......@@ -5,3 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y = generic.o reset.o timer.o
ifndef CONFIG_SPL_BUILD
obj-y += relocate.o
endif
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
......
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
......
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
......
......@@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
reg = readl(&iomuxc_regs->gpr1);
switch (cs_size) {
case CS0_128:
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
reg |= 0x5;
break;
case CS0_64M_CS1_64M:
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
reg |= 0x1B;
break;
case CS0_64M_CS1_32M_CS2_32M:
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
reg |= 0x4B;
break;
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
reg |= 0x249;
break;
default:
printf("Unknown chip select size: %d\n", cs_size);
break;
}
writel(reg, &iomuxc_regs->gpr1);
}
#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{
......
......@@ -596,6 +596,14 @@ int enable_sata_clock(void)
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
void disable_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif
int enable_pcie_clock(void)
......@@ -673,6 +681,36 @@ void hab_caam_clock_enable(unsigned char enable)
}
#endif
static void enable_pll3(void)
{
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
/* make sure pll3 is enabled */
if ((readl(&anatop->usb1_pll_480_ctrl) &
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
/* enable pll's power */
writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
&anatop->usb1_pll_480_ctrl_set);
writel(0x80, &anatop->ana_misc2_clr);
/* wait for pll lock */
while ((readl(&anatop->usb1_pll_480_ctrl) &
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
;
/* disable bypass */
writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
&anatop->usb1_pll_480_ctrl_clr);
/* enable pll output */
writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
&anatop->usb1_pll_480_ctrl_set);
}
}
void enable_thermal_clk(void)
{
enable_pll3();
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
......
......@@ -22,6 +22,8 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
#include <dm.h>
#include <imx_thermal.h>
enum ldo_reg {
LDO_ARM,
......@@ -37,6 +39,19 @@ struct scu_regs {
u32 fpga_rev;
};
#if defined(CONFIG_IMX6_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 1,
.fuse_word = 6,
};
U_BOOT_DEVICE(imx6_thermal) = {
.name = "imx_thermal",
.platdata = &imx6_thermal_plat,
};
#endif
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
......
......@@ -74,6 +74,11 @@ int init_sata(int dev)
return ret;
}
int reset_sata(int dev)
{
return 0;
}
/* On OMAP platforms SATA provides the SCSI subsystem */
void scsi_init(void)
{
......
......@@ -17,6 +17,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
......@@ -134,6 +136,11 @@ int print_cpuinfo(void)
{
u32 cpurev;
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, ret;
#endif
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
......@@ -141,6 +148,21 @@ int print_cpuinfo(void)
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (!ret)
printf("CPU: Temperature %d C\n", cpu_tmp);
else
printf("CPU: Temperature: invalid sensor data\n");
} else {
printf("CPU: Temperature: Can't find sensor device\n");
}
#endif
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
......@@ -180,10 +202,44 @@ u32 get_ahb_clk(void)
return get_periph_clk() / (ahb_podf + 1);
}
#if defined(CONFIG_VIDEO_IPUV3)
void arch_preboot_os(void)
{
#if defined(CONFIG_CMD_SATA)
sata_stop();
#endif
#if defined(CONFIG_VIDEO_IPUV3)
/* disable video before launching O/S */
ipuv3_fb_shutdown();
}
#endif
}
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
reg = readl(&iomuxc_regs->gpr[1]);
switch (cs_size) {
case CS0_128:
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
reg |= 0x5;
break;
case CS0_64M_CS1_64M:
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
reg |= 0x1B;
break;
case CS0_64M_CS1_32M_CS2_32M:
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
reg |= 0x4B;
break;
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
reg |= 0x249;
break;
default:
printf("Unknown chip select size: %d\n", cs_size);
break;
}
writel(reg, &iomuxc_regs->gpr[1]);
}
......@@ -4,5 +4,5 @@
* SPDX-License-Identifier: GPL-2.0+
*/
IMAGE_VERSION 2
IMAGE_VERSION 2
BOOT_FROM sd
......@@ -12,3 +12,8 @@
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
......@@ -202,11 +202,6 @@
*/
#define WBED 1
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
/*
* CSPI register definitions
*/
......@@ -414,8 +409,7 @@ struct weim {
#if defined(CONFIG_MX51)
struct iomuxc {
u32 gpr0;
u32 gpr1;
u32 gpr[2];
u32 omux0;
u32 omux1;
u32 omux2;
......@@ -424,9 +418,7 @@ struct iomuxc {
};
#elif defined(CONFIG_MX53)
struct iomuxc {
u32 gpr0;
u32 gpr1;
u32 gpr2;
u32 gpr[3];
u32 omux0;
u32 omux1;
u32 omux2;
......
......@@ -60,10 +60,12 @@ void enable_uart_clk(unsigned char enable);
int enable_cspi_clock(unsigned char enable, unsigned spi_num);
int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
void disable_sata_clock(void);
int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_thermal_clk(void);
#endif /* __ASM_ARCH_CLOCK_H */
......@@ -332,6 +332,43 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
/* WEIM registers */
struct weim {
u32 cs0gcr1;
u32 cs0gcr2;
u32 cs0rcr1;
u32 cs0rcr2;
u32 cs0wcr1;
u32 cs0wcr2;
u32 cs1gcr1;
u32 cs1gcr2;
u32 cs1rcr1;
u32 cs1rcr2;
u32 cs1wcr1;
u32 cs1wcr2;
u32 cs2gcr1;
u32 cs2gcr2;
u32 cs2rcr1;
u32 cs2rcr2;
u32 cs2wcr1;
u32 cs2wcr2;
u32 cs3gcr1;
u32 cs3gcr2;
u32 cs3rcr1;
u32 cs3rcr2;
u32 cs3wcr1;
u32 cs3wcr2;
u32 unused[12];
u32 wcr;
u32 wiar;
u32 ear;
};
/* System Reset Controller (SRC) */
struct src {
u32 scr;
......
......@@ -26,6 +26,7 @@ u32 get_cpu_rev(void);
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_chipselect_size(int const);
/*
* Initializes on-chip ethernet controllers.
......
......@@ -104,6 +104,11 @@ clr_gd:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
/*
* now relocate vectors
*/
bl relocate_vectors
/* Set up final (full) environment */
......
......@@ -10,6 +10,47 @@
#include <config.h>
#include <linux/linkage.h>
/*
* Default/weak exception vectors relocation routine
*
* This routine covers the standard ARM cases: normal (0x00000000),
* high (0xffff0000) and VBAR. SoCs which do not comply with any of
* the standard cases must provide their own, strong, version.
*/
.section .text.relocate_vectors,"ax",%progbits
.weak relocate_vectors
ENTRY(relocate_vectors)
#ifdef CONFIG_HAS_VBAR
/*
* If the ARM processor has the security extensions,
* use VBAR to relocate the exception vectors.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
#else
/*
* Copy the relocated exception vectors to the
* correct address
* CP15 c1 V bit gives us the location of the vectors:
* 0x00000000 or 0xFFFF0000.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
ands r2, r2, #(1 << 13)
ldreq r1, =0x00000000 /* If V=0 */
ldrne r1, =0xFFFF0000 /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
#endif
bx lr
ENDPROC(relocate_vectors)
/*
* void relocate_code(addr_moni)
*
......@@ -54,34 +95,6 @@ fixnext:
cmp r2, r3
blo fixloop
/*
* Relocate the exception vectors
*/
#ifdef CONFIG_HAS_VBAR
/*
* If the ARM processor has the security extensions,
* use VBAR to relocate the exception vectors.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
#else
/*
* Copy the relocated exception vectors to the
* correct address
* CP15 c1 V bit gives us the location of the vectors:
* 0x00000000 or 0xFFFF0000.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
ands r2, r2, #(1 << 13)
ldreq r1, =0x00000000 /* If V=0 */
ldrne r1, =0xFFFF0000 /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
#endif
relocate_done:
#ifdef __XSCALE__
......@@ -96,9 +109,9 @@ relocate_done:
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
mov pc, lr
mov pc, lr
#else
bx lr
bx lr
#endif
ENDPROC(relocate_code)
......@@ -173,7 +173,7 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = {
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
......@@ -196,13 +196,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
......
......@@ -302,7 +302,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
......@@ -325,13 +325,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif
......
......@@ -98,9 +98,6 @@ int sata_initialize(void)
/* Make sure this gpio has logical 0 value */
gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
udelay(100);
cm_fx6_sata_power(0);
mdelay(250);
cm_fx6_sata_power(1);