Commit df33f6b4 authored by Timur Tabi's avatar Timur Tabi Committed by Kim Phillips
Browse files

Update SCCR programming in cpu_init_f() to support all 83xx processors



Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors.  The code to update some bitfields was
compiled only on some processors.  Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.
Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
parent 95462669
...@@ -83,20 +83,30 @@ void cpu_init_f (volatile immap_t * im) ...@@ -83,20 +83,30 @@ void cpu_init_f (volatile immap_t * im)
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
#endif #endif
#ifdef CONFIG_MPC834X
#ifdef CFG_SCCR_TSEC1CM #ifdef CFG_SCCR_TSEC1CM
/* TSEC1 clock mode */ /* TSEC1 clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
#endif #endif
#ifdef CFG_SCCR_TSEC2CM #ifdef CFG_SCCR_TSEC2CM
/* TSEC2 & I2C1 clock mode */ /* TSEC2 & I2C1 clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
#endif #endif
#ifdef CFG_SCCR_TSEC1ON
/* TSEC1 clock switch */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
#endif
#ifdef CFG_SCCR_TSEC2ON
/* TSEC2 clock switch */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
#endif
#ifdef CFG_SCCR_USBMPHCM #ifdef CFG_SCCR_USBMPHCM
/* USB MPH clock mode */ /* USB MPH clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
#endif #endif
#endif /* CONFIG_MPC834X */
#ifdef CFG_SCCR_PCICM #ifdef CFG_SCCR_PCICM
/* PCI & DMA clock mode */ /* PCI & DMA clock mode */
......
...@@ -602,7 +602,9 @@ ...@@ -602,7 +602,9 @@
#define SCCR_TSEC1CM_3 0xC0000000 #define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC1ON 0x20000000 #define SCCR_TSEC1ON 0x20000000
#define SCCR_TSEC1ON_SHIFT 29
#define SCCR_TSEC2ON 0x10000000 #define SCCR_TSEC2ON 0x10000000
#define SCCR_TSEC2ON_SHIFT 28
#endif #endif
......
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