Commit df482650 authored by Stephan Linz's avatar Stephan Linz Committed by Joe Hershberger

net: ll_temac: Add LL TEMAC driver to u-boot

Xilinx LocalLink Tri-Mode Ether MAC driver can be
used by Xilinx Microblaze or Xilinx ppc405/440 in
SDMA and FIFO mode. DCR or XPS bus can be used.

The driver uses and requires MII and PHYLIB.

CP: 4 warnings: 'Use of volatile is usually wrong'
I won't fix this, because it depends on the network
driver subsystem.
Reported-by: default avatarMichal Simek <monstr@monstr.eu>
Signed-off-by: default avatarStephan Linz <linz@li-pro.net>
parent 1295f08c
......@@ -77,6 +77,8 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
......
/*
* Xilinx xps_ll_temac ethernet driver for u-boot
*
* supports SDMA or FIFO access and MDIO bus communication
*
* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2008 - 2011 PetaLogix
*
* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
* Copyright (C) 2008 Nissin Systems Co.,Ltd.
* March 2008 created
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* [0]: http://www.xilinx.com/support/documentation
*
* [S]: [0]/ip_documentation/xps_ll_temac.pdf
* [A]: [0]/application_notes/xapp1041.pdf
*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <asm/io.h>
#include <miiphy.h>
#include "xilinx_ll_temac.h"
#include "xilinx_ll_temac_fifo.h"
#include "xilinx_ll_temac_sdma.h"
#include "xilinx_ll_temac_mdio.h"
#if !defined(CONFIG_MII)
# error "LL_TEMAC requires MII -- missing CONFIG_MII"
#endif
#if !defined(CONFIG_PHYLIB)
# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB"
#endif
struct ll_temac_info {
int flags;
unsigned long base_addr;
unsigned long ctrl_addr;
char *devname;
unsigned int phyaddr;
char *mdio_busname;
};
/* Ethernet interface ready status */
int ll_temac_check_status(struct temac_reg *regs, u32 mask)
{
unsigned timeout = 50; /* 1usec * 50 = 50usec */
/*
* Quote from LL TEMAC documentation: The bits in the RDY
* register are asserted when there is no access in progress.
* When an access is in progress, a bit corresponding to the
* type of access is automatically de-asserted. The bit is
* automatically re-asserted when the access is complete.
*/
while (timeout && (!(in_be32(&regs->rdy) & mask))) {
timeout--;
udelay(1);
}
if (!timeout) {
printf("%s: Timeout on 0x%08x @%p\n", __func__,
mask, &regs->rdy);
return 1;
}
return 0;
}
/*
* Indirect write to ll_temac.
*
* http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
* page 23, second paragraph, The use of CTL0 register or CTL1 register
*/
int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data)
{
out_be32(&regs->lsw, (reg_data & MLSW_MASK));
out_be32(&regs->ctl, CTL_WEN | (regn & CTL_ADDR_MASK));
if (ll_temac_check_status(regs, RSE_CFG_WR))
return 0;
return 1;
}
/*
* Indirect read from ll_temac.
*
* http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf
* page 23, second paragraph, The use of CTL0 register or CTL1 register
*/
int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data)
{
out_be32(&regs->ctl, (regn & CTL_ADDR_MASK));
if (ll_temac_check_status(regs, RSE_CFG_RR))
return 0;
*reg_data = in_be32(&regs->lsw) & MLSW_MASK;
return 1;
}
/* setting sub-controller and ll_temac to proper setting */
static int ll_temac_setup_ctrl(struct eth_device *dev)
{
struct ll_temac *ll_temac = dev->priv;
struct temac_reg *regs = (struct temac_reg *)dev->iobase;
if (ll_temac->ctrlreset && ll_temac->ctrlreset(dev))
return 0;
if (ll_temac->ctrlinit && ll_temac->ctrlinit(dev))
return 0;
/* Promiscuous mode disable */
if (!ll_temac_indirect_set(regs, TEMAC_AFM, 0))
return 0;
/* Enable Receiver - RX bit */
if (!ll_temac_indirect_set(regs, TEMAC_RCW1, RCW1_RX))
return 0;
/* Enable Transmitter - TX bit */
if (!ll_temac_indirect_set(regs, TEMAC_TC, TC_TX))
return 0;
return 1;
}
/*
* Configure ll_temac based on negotiated speed and duplex
* reported by PHY handling code
*/
static int ll_temac_adjust_link(struct eth_device *dev)
{
unsigned int speed, emmc_reg;
struct temac_reg *regs = (struct temac_reg *)dev->iobase;
struct ll_temac *ll_temac = dev->priv;
struct phy_device *phydev = ll_temac->phydev;
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
return 0;
}
switch (phydev->speed) {
case 1000:
speed = EMMC_LSPD_1000;
break;
case 100:
speed = EMMC_LSPD_100;
break;
case 10:
speed = EMMC_LSPD_10;
break;
default:
return 0;
}
if (!ll_temac_indirect_get(regs, TEMAC_EMMC, &emmc_reg))
return 0;
emmc_reg &= ~EMMC_LSPD_MASK;
emmc_reg |= speed;
if (!ll_temac_indirect_set(regs, TEMAC_EMMC, emmc_reg))
return 0;
printf("%s: PHY is %s with %dbase%s, %s%s\n",
dev->name, phydev->drv->name,
phydev->speed, (phydev->port == PORT_TP) ? "T" : "X",
(phydev->duplex) ? "FDX" : "HDX",
(phydev->port == PORT_OTHER) ? ", unkown mode" : "");
return 1;
}
/* setup mac addr */
static int ll_temac_setup_mac_addr(struct eth_device *dev)
{
struct temac_reg *regs = (struct temac_reg *)dev->iobase;
u32 val;
/* set up unicast MAC address filter */
val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
val &= UAW0_UADDR_MASK;
if (!ll_temac_indirect_set(regs, TEMAC_UAW0, val))
return 1;
val = ((dev->enetaddr[5] << 8) | dev->enetaddr[4]);
val &= UAW1_UADDR_MASK;
if (!ll_temac_indirect_set(regs, TEMAC_UAW1, val))
return 1;
return 0;
}
/* halt device */
static void ll_temac_halt(struct eth_device *dev)
{
struct ll_temac *ll_temac = dev->priv;
struct temac_reg *regs = (struct temac_reg *)dev->iobase;
/* Disable Receiver */
ll_temac_indirect_set(regs, TEMAC_RCW0, 0);
/* Disable Transmitter */
ll_temac_indirect_set(regs, TEMAC_TC, 0);
if (ll_temac->ctrlhalt)
ll_temac->ctrlhalt(dev);
/* Shut down the PHY, as needed */
phy_shutdown(ll_temac->phydev);
}
static int ll_temac_init(struct eth_device *dev, bd_t *bis)
{
struct ll_temac *ll_temac = dev->priv;
printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",
dev->name, dev->index, dev->iobase);
if (!ll_temac_setup_ctrl(dev))
return -1;
/* Start up the PHY */
phy_startup(ll_temac->phydev);
if (!ll_temac_adjust_link(dev)) {
ll_temac_halt(dev);
return -1;
}
/* If there's no link, fail */
return ll_temac->phydev->link ? 0 : -1;
}
/*
* Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
*/
static int ll_temac_phy_init(struct eth_device *dev)
{
struct ll_temac *ll_temac = dev->priv;
struct phy_device *phydev;
unsigned int supported = PHY_GBIT_FEATURES;
/* interface - look at driver/net/tsec.c */
phydev = phy_connect(ll_temac->bus, ll_temac->phyaddr,
dev, PHY_INTERFACE_MODE_NONE);
phydev->supported &= supported;
phydev->advertising = phydev->supported;
ll_temac->phydev = phydev;
phy_config(phydev);
return 1;
}
/*
* Initialize a single ll_temac devices
*
* Returns the result of ll_temac phy interface that were initialized
*/
int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf)
{
struct eth_device *dev;
struct ll_temac *ll_temac;
dev = calloc(1, sizeof(*dev));
if (dev == NULL)
return 0;
ll_temac = calloc(1, sizeof(struct ll_temac));
if (ll_temac == NULL) {
free(dev);
return 0;
}
/* use given name or generate its own unique name */
if (devinf->devname) {
strncpy(dev->name, devinf->devname, NAMESIZE);
} else {
snprintf(dev->name, NAMESIZE, "lltemac.%lx", devinf->base_addr);
devinf->devname = dev->name;
}
dev->iobase = devinf->base_addr;
dev->priv = ll_temac;
dev->init = ll_temac_init;
dev->halt = ll_temac_halt;
dev->write_hwaddr = ll_temac_setup_mac_addr;
ll_temac->ctrladdr = devinf->ctrl_addr;
if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_PLB) {
#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405)
if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_DCR) {
ll_temac_collect_xldcr_sdma_reg_addr(dev);
ll_temac->in32 = ll_temac_xldcr_in32;
ll_temac->out32 = ll_temac_xldcr_out32;
} else
#endif
{
ll_temac_collect_xlplb_sdma_reg_addr(dev);
ll_temac->in32 = ll_temac_xlplb_in32;
ll_temac->out32 = ll_temac_xlplb_out32;
}
ll_temac->ctrlinit = ll_temac_init_sdma;
ll_temac->ctrlhalt = ll_temac_halt_sdma;
ll_temac->ctrlreset = ll_temac_reset_sdma;
dev->recv = ll_temac_recv_sdma;
dev->send = ll_temac_send_sdma;
} else {
ll_temac->in32 = NULL;
ll_temac->out32 = NULL;
ll_temac->ctrlinit = NULL;
ll_temac->ctrlhalt = NULL;
ll_temac->ctrlreset = ll_temac_reset_fifo;
dev->recv = ll_temac_recv_fifo;
dev->send = ll_temac_send_fifo;
}
/* Link to specified MDIO bus */
strncpy(ll_temac->mdio_busname, devinf->mdio_busname, MDIO_NAME_LEN);
ll_temac->bus = miiphy_get_dev_by_name(ll_temac->mdio_busname);
/* Looking for a valid PHY address if it is not yet set */
if (devinf->phyaddr == -1)
ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus);
else
ll_temac->phyaddr = devinf->phyaddr;
eth_register(dev);
/* Try to initialize PHY here, and return */
return ll_temac_phy_init(dev);
}
/*
* Initialize a single ll_temac device with its mdio bus behind ll_temac
*
* Returns 1 if the ll_temac device and the mdio bus were initialized
* otherwise returns 0
*/
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr)
{
struct ll_temac_info devinf;
struct ll_temac_mdio_info mdioinf;
int ret;
/* prepare the internal driver informations */
devinf.flags = flags;
devinf.base_addr = base_addr;
devinf.ctrl_addr = ctrl_addr;
devinf.devname = NULL;
devinf.phyaddr = -1;
mdioinf.name = devinf.mdio_busname = NULL;
mdioinf.regs = (struct temac_reg *)devinf.base_addr;
ret = xilinx_ll_temac_mdio_initialize(bis, &mdioinf);
if (ret >= 0) {
/*
* If there was no MDIO bus name then take over the
* new automaticaly generated by the MDIO init code.
*/
if (mdioinf.name != devinf.mdio_busname)
devinf.mdio_busname = mdioinf.name;
ret = xilinx_ll_temac_initialize(bis, &devinf);
if (ret > 0)
return 1;
}
return 0;
}
/*
* Xilinx xps_ll_temac ethernet driver for u-boot
*
* LL_TEMAC interface
*
* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2008 - 2011 PetaLogix
*
* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
* Copyright (C) 2008 Nissin Systems Co.,Ltd.
* March 2008 created
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* [0]: http://www.xilinx.com/support/documentation
*
* [S]: [0]/ip_documentation/xps_ll_temac.pdf
* [A]: [0]/application_notes/xapp1041.pdf
*/
#ifndef _XILINX_LL_TEMAC_
#define _XILINX_LL_TEMAC_
#include <config.h>
#include <net.h>
#include <phy.h>
#include <miiphy.h>
#include <asm/types.h>
#include <asm/byteorder.h>
#include "xilinx_ll_temac_sdma.h"
#if !defined(__BIG_ENDIAN)
# error LL_TEMAC requires big endianess
#endif
/*
* TEMAC Memory and Register Definition
*
* [1]: [0]/ip_documentation/xps_ll_temac.pdf
* page 19, Memory and Register Descriptions
*/
struct temac_reg {
/* direct soft registers (low part) */
u32 raf; /* Reset and Address Filter */
u32 tpf; /* Transmit Pause Frame */
u32 ifgp; /* Transmit Inter Frame Gap Adjustment */
u32 is; /* Interrupt Status */
u32 ip; /* Interrupt Pending */
u32 ie; /* Interrupt Enable */
u32 ttag; /* Transmit VLAN Tag */
u32 rtag; /* Receive VLAN Tag */
/* hard TEMAC registers */
u32 msw; /* Most Significant Word Data */
u32 lsw; /* Least Significant Word Data */
u32 ctl; /* Control */
u32 rdy; /* Ready Status */
/* direct soft registers (high part) */
u32 uawl; /* Unicast Address Word Lower */
u32 uawu; /* Unicast Address Word Upper */
u32 tpid0; /* VLAN TPID Word 0 */
u32 tpid1; /* VLAN TPID Word 1 */
};
/* Reset and Address Filter Registers (raf), [1] p25 */
#define RAF_SR (1 << 13)
#define RAF_EMFE (1 << 12)
#define RAF_NFE (1 << 11)
#define RAF_RVSTM_POS 9
#define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS)
#define RAF_TVSTM_POS 7
#define RAF_TVSTM_MASK (3 << RAF_TVSTM_POS)
#define RAF_RVTM_POS 5
#define RAF_RVTM_MASK (3 << RAF_RVTM_POS)
#define RAF_TVTM_POS 3
#define RAF_TVTM_MASK (3 << RAF_TVTM_POS)
#define RAF_BCREJ (1 << 2)
#define RAF_MCREJ (1 << 1)
#define RAF_HTRST (1 << 0)
/* Transmit Pause Frame Registers (tpf), [1] p28 */
#define TPF_TPFV_POS 0
#define TPF_TPFV_MASK (0xFFFF << TPF_TPFV_POS)
/* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */
#define IFGP_POS 0
#define IFGP_MASK (0xFF << IFGP_POS)
/* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */
#define ISPE_MR (1 << 7)
#define ISPE_RDL (1 << 6)
#define ISPE_TC (1 << 5)
#define ISPE_RFO (1 << 4)
#define ISPE_RR (1 << 3)
#define ISPE_RC (1 << 2)
#define ISPE_AN (1 << 1)
#define ISPE_HAC (1 << 0)
/* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */
#define TRTAG_TPID_POS 16
#define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS)
#define TRTAG_PRIO_POS 13
#define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS)
#define TRTAG_CFI (1 << 12)
#define TRTAG_VID_POS 0
#define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS)
/* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */
#define MLSW_POS 0
#define MLSW_MASK (~0UL << MLSW_POS)
/* LSW Data Register for PHY addresses (lsw), [1] p66 */
#define LSW_REGAD_POS 0
#define LSW_REGAD_MASK (0x1F << LSW_REGAD_POS)
#define LSW_PHYAD_POS 5
#define LSW_PHYAD_MASK (0x1F << LSW_PHYAD_POS)
/* LSW Data Register for PHY data (lsw), [1] p66 */
#define LSW_REGDAT_POS 0
#define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS)
/* Control Register (ctl), [1] p47 */
#define CTL_WEN (1 << 15)
#define CTL_ADDR_POS 0
#define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS)
/* Ready Status Register Ethernet (rdy), [1] p48 */
#define RSE_HACS_RDY (1 << 14)
#define RSE_CFG_WR (1 << 6)
#define RSE_CFG_RR (1 << 5)
#define RSE_AF_WR (1 << 4)
#define RSE_AF_RR (1 << 3)
#define RSE_MIIM_WR (1 << 2)
#define RSE_MIIM_RR (1 << 1)
#define RSE_FABR_RR (1 << 0)
/* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */
#define UAWL_UADDR_POS 0
#define UAWL_UADDR_MASK (~0UL << UAWL_UADDR_POS)
#define UAWU_UADDR_POS 0
#define UAWU_UADDR_MASK (0xFFFF << UAWU_UADDR_POS)
/* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */
#define TPID0_V0_POS 0
#define TPID0_V0_MASK (0xFFFF << TPID0_V0_POS)
#define TPID0_V1_POS 16
#define TPID0_V1_MASK (0xFFFF << TPID0_V1_POS)
#define TPID1_V2_POS 0
#define TPID1_V2_MASK (0xFFFF << TPID1_V2_POS)
#define TPID1_V3_POS 16
#define TPID1_V3_MASK (0xFFFF << TPID1_V3_POS)
/*
* TEMAC Indirectly Addressable Register Index Enumeration
*
* [0]: http://www.xilinx.com/support/documentation
*
* [1]: [0]/ip_documentation/xps_ll_temac.pdf
* page 23, PLB Indirectly Addressable TEMAC Registers
*/
enum temac_ctrl {
TEMAC_RCW0 = 0x200,
TEMAC_RCW1 = 0x240,
TEMAC_TC = 0x280,
TEMAC_FCC = 0x2C0,
TEMAC_EMMC = 0x300,
TEMAC_PHYC = 0x320,
TEMAC_MC = 0x340,
TEMAC_UAW0 = 0x380,
TEMAC_UAW1 = 0x384,
TEMAC_MAW0 = 0x388,
TEMAC_MAW1 = 0x38C,
TEMAC_AFM = 0x390,
TEMAC_TIS = 0x3A0,
TEMAC_TIE = 0x3A4,
TEMAC_MIIMWD = 0x3B0,
TEMAC_MIIMAI = 0x3B4
};
/* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */
#define RCW0_PADDR_POS 0
#define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS)
#define RCW1_RST (1 << 31)
#define RCW1_JUM (1 << 30)
#define RCW1_FCS (1 << 29)
#define RCW1_RX (1 << 28)
#define RCW1_VLAN (1 << 27)
#define RCW1_HD (1 << 26)
#define RCW1_LT_DIS (1 << 25)
#define RCW1_PADDR_POS 0
#define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS)
/* Transmit Configuration Registers (TC), [1] p52 */
#define TC_RST (1 << 31)
#define TC_JUM (1 << 30)
#define TC_FCS (1 << 29)
#define TC_TX (1 << 28)
#define TC_VLAN (1 << 27)
#define TC_HD (1 << 26)
#define TC_IFG (1 << 25)
/* Flow Control Configuration Registers (FCC), [1] p54 */
#define FCC_FCTX (1 << 30)
#define FCC_FCRX (1 << 29)
/* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */
#define EMMC_LSPD_POS 30
#define EMMC_LSPD_MASK (3 << EMMC_LSPD_POS)
#define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS)
#define EMMC_LSPD_100 (1 << EMMC_LSPD_POS)
#define EMMC_LSPD_10 0
#define EMMC_RGMII (1 << 29)
#define EMMC_SGMII (1 << 28)