Commit e22b1a54 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

parents 8889e984 e16b604e
......@@ -344,5 +344,13 @@ void smp_kick_all_cpus(void)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
/*
* LS1 STANDBYWFE is not captured outside the ARM module in the soc.
* So add a delay to wait bootrom execute WFE.
*/
udelay(1);
asm volatile("sev");
}
#endif
......@@ -10,6 +10,7 @@
#include <fsl_ddrc_version.h>
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CONFIG_SYS_CACHELINE_SIZE 64
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
......@@ -63,6 +64,9 @@
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
......
......@@ -54,6 +54,92 @@ enum {
GE1_CLK125,
};
#ifdef CONFIG_LS102XA_NS_ACCESS
static struct csu_ns_dev ns_dev[] = {
{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
{ CSU_CSLX_OCRAM, CSU_ALL_RW },
{ CSU_CSLX_GIC, CSU_ALL_RW },
{ CSU_CSLX_PCIE1, CSU_ALL_RW },
{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
{ CSU_CSLX_PCIE2, CSU_ALL_RW },
{ CSU_CSLX_SATA, CSU_ALL_RW },
{ CSU_CSLX_USB3, CSU_ALL_RW },
{ CSU_CSLX_SERDES, CSU_ALL_RW },
{ CSU_CSLX_QDMA, CSU_ALL_RW },
{ CSU_CSLX_LPUART2, CSU_ALL_RW },
{ CSU_CSLX_LPUART1, CSU_ALL_RW },
{ CSU_CSLX_LPUART4, CSU_ALL_RW },
{ CSU_CSLX_LPUART3, CSU_ALL_RW },
{ CSU_CSLX_LPUART6, CSU_ALL_RW },
{ CSU_CSLX_LPUART5, CSU_ALL_RW },
{ CSU_CSLX_DSPI2, CSU_ALL_RW },
{ CSU_CSLX_DSPI1, CSU_ALL_RW },
{ CSU_CSLX_QSPI, CSU_ALL_RW },
{ CSU_CSLX_ESDHC, CSU_ALL_RW },
{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
{ CSU_CSLX_IFC, CSU_ALL_RW },
{ CSU_CSLX_I2C1, CSU_ALL_RW },
{ CSU_CSLX_USB2, CSU_ALL_RW },
{ CSU_CSLX_I2C3, CSU_ALL_RW },
{ CSU_CSLX_I2C2, CSU_ALL_RW },
{ CSU_CSLX_DUART2, CSU_ALL_RW },
{ CSU_CSLX_DUART1, CSU_ALL_RW },
{ CSU_CSLX_WDT2, CSU_ALL_RW },
{ CSU_CSLX_WDT1, CSU_ALL_RW },
{ CSU_CSLX_EDMA, CSU_ALL_RW },
{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
{ CSU_CSLX_DDR, CSU_ALL_RW },
{ CSU_CSLX_QUICC, CSU_ALL_RW },
{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
{ CSU_CSLX_SFP, CSU_ALL_RW },
{ CSU_CSLX_TMU, CSU_ALL_RW },
{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
{ CSU_CSLX_GPIO2, CSU_ALL_RW },
{ CSU_CSLX_GPIO1, CSU_ALL_RW },
{ CSU_CSLX_GPIO4, CSU_ALL_RW },
{ CSU_CSLX_GPIO3, CSU_ALL_RW },
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
{ CSU_CSLX_CSU, CSU_ALL_RW },
{ CSU_CSLX_ASRC, CSU_ALL_RW },
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
{ CSU_CSLX_SAI2, CSU_ALL_RW },
{ CSU_CSLX_SAI1, CSU_ALL_RW },
{ CSU_CSLX_SAI4, CSU_ALL_RW },
{ CSU_CSLX_SAI3, CSU_ALL_RW },
{ CSU_CSLX_FTM2, CSU_ALL_RW },
{ CSU_CSLX_FTM1, CSU_ALL_RW },
{ CSU_CSLX_FTM4, CSU_ALL_RW },
{ CSU_CSLX_FTM3, CSU_ALL_RW },
{ CSU_CSLX_FTM6, CSU_ALL_RW },
{ CSU_CSLX_FTM5, CSU_ALL_RW },
{ CSU_CSLX_FTM8, CSU_ALL_RW },
{ CSU_CSLX_FTM7, CSU_ALL_RW },
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
{ CSU_CSLX_EPU, CSU_ALL_RW },
{ CSU_CSLX_GDI, CSU_ALL_RW },
{ CSU_CSLX_DDI, CSU_ALL_RW },
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
};
#endif
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
......@@ -292,6 +378,12 @@ void board_init_f(ulong dummy)
dram_init();
/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LS102XA_NS_ACCESS
enable_devices_ns_access(&ns_dev[4], 1);
enable_devices_ns_access(&ns_dev[7], 1);
#endif
board_init_r(NULL, 0);
}
#endif
......@@ -444,92 +536,6 @@ int misc_init_r(void)
return 0;
}
#ifdef CONFIG_LS102XA_NS_ACCESS
static struct csu_ns_dev ns_dev[] = {
{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
{ CSU_CSLX_OCRAM, CSU_ALL_RW },
{ CSU_CSLX_GIC, CSU_ALL_RW },
{ CSU_CSLX_PCIE1, CSU_ALL_RW },
{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
{ CSU_CSLX_PCIE2, CSU_ALL_RW },
{ CSU_CSLX_SATA, CSU_ALL_RW },
{ CSU_CSLX_USB3, CSU_ALL_RW },
{ CSU_CSLX_SERDES, CSU_ALL_RW },
{ CSU_CSLX_QDMA, CSU_ALL_RW },
{ CSU_CSLX_LPUART2, CSU_ALL_RW },
{ CSU_CSLX_LPUART1, CSU_ALL_RW },
{ CSU_CSLX_LPUART4, CSU_ALL_RW },
{ CSU_CSLX_LPUART3, CSU_ALL_RW },
{ CSU_CSLX_LPUART6, CSU_ALL_RW },
{ CSU_CSLX_LPUART5, CSU_ALL_RW },
{ CSU_CSLX_DSPI2, CSU_ALL_RW },
{ CSU_CSLX_DSPI1, CSU_ALL_RW },
{ CSU_CSLX_QSPI, CSU_ALL_RW },
{ CSU_CSLX_ESDHC, CSU_ALL_RW },
{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
{ CSU_CSLX_IFC, CSU_ALL_RW },
{ CSU_CSLX_I2C1, CSU_ALL_RW },
{ CSU_CSLX_USB2, CSU_ALL_RW },
{ CSU_CSLX_I2C3, CSU_ALL_RW },
{ CSU_CSLX_I2C2, CSU_ALL_RW },
{ CSU_CSLX_DUART2, CSU_ALL_RW },
{ CSU_CSLX_DUART1, CSU_ALL_RW },
{ CSU_CSLX_WDT2, CSU_ALL_RW },
{ CSU_CSLX_WDT1, CSU_ALL_RW },
{ CSU_CSLX_EDMA, CSU_ALL_RW },
{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
{ CSU_CSLX_DDR, CSU_ALL_RW },
{ CSU_CSLX_QUICC, CSU_ALL_RW },
{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
{ CSU_CSLX_SFP, CSU_ALL_RW },
{ CSU_CSLX_TMU, CSU_ALL_RW },
{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
{ CSU_CSLX_GPIO2, CSU_ALL_RW },
{ CSU_CSLX_GPIO1, CSU_ALL_RW },
{ CSU_CSLX_GPIO4, CSU_ALL_RW },
{ CSU_CSLX_GPIO3, CSU_ALL_RW },
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
{ CSU_CSLX_CSU, CSU_ALL_RW },
{ CSU_CSLX_ASRC, CSU_ALL_RW },
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
{ CSU_CSLX_SAI2, CSU_ALL_RW },
{ CSU_CSLX_SAI1, CSU_ALL_RW },
{ CSU_CSLX_SAI4, CSU_ALL_RW },
{ CSU_CSLX_SAI3, CSU_ALL_RW },
{ CSU_CSLX_FTM2, CSU_ALL_RW },
{ CSU_CSLX_FTM1, CSU_ALL_RW },
{ CSU_CSLX_FTM4, CSU_ALL_RW },
{ CSU_CSLX_FTM3, CSU_ALL_RW },
{ CSU_CSLX_FTM6, CSU_ALL_RW },
{ CSU_CSLX_FTM5, CSU_ALL_RW },
{ CSU_CSLX_FTM8, CSU_ALL_RW },
{ CSU_CSLX_FTM7, CSU_ALL_RW },
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
{ CSU_CSLX_EPU, CSU_ALL_RW },
{ CSU_CSLX_GDI, CSU_ALL_RW },
{ CSU_CSLX_DDI, CSU_ALL_RW },
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
};
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
......
This diff is collapsed.
......@@ -406,10 +406,19 @@ static void kick_trng(int ent_delay)
sec_out32(&rng->rtsdctl, val);
/* min. freq. count, equal to 1/4 of the entropy sample length */
sec_out32(&rng->rtfreqmin, ent_delay >> 2);
/* max. freq. count, equal to 8 times the entropy sample length */
sec_out32(&rng->rtfreqmax, ent_delay << 3);
/* disable maximum frequency count */
sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
/* read the control register */
val = sec_in32(&rng->rtmctl);
/*
* select raw sampling in both entropy shifter
* and statistical checker
*/
sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
/* put RNG4 into run mode */
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
sec_clrbits32(&val, RTMCTL_PRGM);
/* write back the control register */
sec_out32(&rng->rtmctl, val);
}
static int rng_init(void)
......@@ -459,14 +468,16 @@ static int rng_init(void)
int sec_init(void)
{
int ret = 0;
#ifdef CONFIG_PHYS_64BIT
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT);
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#ifdef CONFIG_PHYS_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
ret = jr_init();
if (ret < 0) {
printf("SEC initialization failed\n");
......
......@@ -21,6 +21,8 @@
#define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */
#define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */
#define MCFGR_PS_SHIFT 16
#define MCFGR_AWCACHE_SHIFT 8
#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
#define JR_INTMASK 0x00000001
#define JRCR_RESET 0x01
#define JRINT_ERR_HALT_INPROGRESS 0x4
......
......@@ -60,27 +60,26 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
return;
}
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
err = fdt_setprop_u32(blob, crypto_node, "fsl,num-channels",
sec_rev_prop_list[sec_idx].num_channels);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask",
&val, 4);
err = fdt_setprop_u32(blob, crypto_node, "fsl,descriptor-types-mask",
sec_rev_prop_list[sec_idx].descriptor_types_mask);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
err = fdt_setprop_u32(blob, crypto_node, "fsl,exec-units-mask",
sec_rev_prop_list[sec_idx].exec_units_mask);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
err = fdt_setprop_u32(blob, crypto_node, "fsl,channel-fifo-len",
sec_rev_prop_list[sec_idx].channel_fifo_len);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
......@@ -155,8 +154,7 @@ static void fdt_fixup_crypto_era(void *blob, u32 era)
return;
}
err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
sizeof(era));
err = fdt_setprop_u32(blob, crypto_node, "fsl,sec-era", era);
if (err < 0) {
printf("ERROR: could not set fsl,sec-era property: %s\n",
fdt_strerror(err));
......
......@@ -535,7 +535,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
* which is currently STEP_ASSIGN_ADDRESSES.
*/
populate_memctl_options(
timing_params[i].all_dimms_registered,
&timing_params[i],
&pinfo->memctl_opts[i],
pinfo->dimm_params[i], i);
/*
......
......@@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
return 0;
}
unsigned int populate_memctl_options(int all_dimms_registered,
unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
......@@ -640,7 +640,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
popts->ba_intlv_ctl = 0;
/* Memory Organization Parameters */
popts->registered_dimm_en = all_dimms_registered;
popts->registered_dimm_en = common_dimm->all_dimms_registered;
/* Operational Mode Paramters */
......@@ -778,9 +778,11 @@ unsigned int populate_memctl_options(int all_dimms_registered,
* Set this to 0 for global auto precharge
* The value of 0x100 has been used for DDR1, DDR2, DDR3.
* It is not wrong. Any value should be OK. The performance depends on
* applications. There is no one good value for all.
* applications. There is no one good value for all. One way to set
* is to use 1/4 of refint value.
*/
popts->bstopre = 0x100;
popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
>> 2;
/*
* Window for four activates -- tFAW
......
......@@ -10,14 +10,18 @@
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dpbp.h>
int dpbp_open(struct fsl_mc_io *mc_io, int dpbp_id, uint16_t *token)
int dpbp_open(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
int dpbp_id,
uint16_t *token)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN,
MC_CMD_PRI_LOW, 0);
cmd_flags,
0);
DPBP_CMD_OPEN(cmd, dpbp_id);
/* send command to mc*/
......@@ -31,55 +35,66 @@ int dpbp_open(struct fsl_mc_io *mc_io, int dpbp_id, uint16_t *token)
return err;
}
int dpbp_close(struct fsl_mc_io *mc_io, uint16_t token)
int dpbp_close(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, MC_CMD_PRI_HIGH,
cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpbp_enable(struct fsl_mc_io *mc_io, uint16_t token)
int dpbp_enable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, MC_CMD_PRI_LOW,
cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpbp_disable(struct fsl_mc_io *mc_io, uint16_t token)
int dpbp_disable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpbp_reset(struct fsl_mc_io *mc_io, uint16_t token)
int dpbp_reset(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpbp_get_attributes(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
struct dpbp_attr *attr)
{
......@@ -88,7 +103,8 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io,
/* prepare command */
cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
......
......@@ -8,14 +8,18 @@
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dpio.h>
int dpio_open(struct fsl_mc_io *mc_io, int dpio_id, uint16_t *token)
int dpio_open(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
int dpio_id,
uint16_t *token)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
MC_CMD_PRI_LOW, 0);
cmd_flags,
0);
DPIO_CMD_OPEN(cmd, dpio_id);
/* send command to mc*/
......@@ -29,56 +33,68 @@ int dpio_open(struct fsl_mc_io *mc_io, int dpio_id, uint16_t *token)
return 0;
}
int dpio_close(struct fsl_mc_io *mc_io, uint16_t token)
int dpio_close(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
MC_CMD_PRI_HIGH, token);
cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpio_enable(struct fsl_mc_io *mc_io, uint16_t token)
int dpio_enable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpio_disable(struct fsl_mc_io *mc_io, uint16_t token)
int dpio_disable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
MC_CMD_PRI_LOW,
cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpio_reset(struct fsl_mc_io *mc_io, uint16_t token)
int dpio_reset(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
int dpio_get_attributes(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
struct dpio_attr *attr)
{
......@@ -87,7 +103,7 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io,
/* prepare command */
cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
MC_CMD_PRI_LOW,
cmd_flags,
token);
/* send command to mc*/
......
......@@ -7,14 +7,17 @@
#include <fsl-mc/fsl_dpmng.h>
#include "fsl_dpmng_cmd.h"
int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info)
int mc_get_version(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
struct mc_version *mc_ver_info)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
MC_CMD_PRI_LOW, 0);
cmd_flags,
0);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
......
This diff is collapsed.
......@@ -11,14 +11,17 @@
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dprc.h>
int dprc_get_container_id(struct fsl_mc_io *mc_io, int *container_id)
int dprc_get_container_id(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
int *container_id)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
MC_CMD_PRI_LOW, 0);
cmd_flags,
0);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
......@@ -31,13 +34,16 @@ int dprc_get_container_id(struct fsl_mc_io *mc_io, int *container_id)
return 0;
}
int dprc_open(struct fsl_mc_io *mc_io, int container_id, uint16_t *token)
int dprc_open(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
int container_id,
uint16_t *token)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, MC_CMD_PRI_LOW,
cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags,
0);
DPRC_CMD_OPEN(cmd, container_id);
......@@ -52,12 +58,14 @@ int dprc_open(struct fsl_mc_io *mc_io, int container_id, uint16_t *token)
return 0;
}
int dprc_close(struct fsl_mc_io *mc_io, uint16_t token)
int dprc_close(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
{
struct mc_command cmd = { 0 };
/* prepare command */
cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, MC_CMD_PRI_HIGH,
cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags,
token);
/* send command to mc*/
......@@ -65,6 +73,7 @@ int dprc_close(struct fsl_mc_io *mc_io, uint16_t token)
}
int dprc_reset_container(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
int child_container_id)
{
......@@ -72,7 +81,8 @@ int dprc_reset_container(struct fsl_mc_io *mc_io,
/* prepare command */
cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);
DPRC_CMD_RESET_CONTAINER(cmd, child_container_id);
/* send command to mc*/
......@@ -80,6 +90,7 @@ int dprc_reset_container(struct fsl_mc_io *mc_io,
}
int dprc_get_attributes(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
struct dprc_attributes *attr)
{
......@@ -88,7 +99,7 @@ int dprc_get_attributes(struct fsl_mc_io *mc_io,
/* prepare command */
cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR,
MC_CMD_PRI_LOW,
cmd_flags,
token);
/* send command to mc*/
......@@ -102,14 +113,18 @@ int dprc_get_attributes(struct fsl_mc_io *mc_io,
return 0;
}
int dprc_get_obj_count(struct fsl_mc_io *mc_io, uint16_t token, int *obj_count)
int dprc_get_obj_count(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
int *obj_count)
{
struct mc_command cmd = { 0 };
int err;
/* prepare command */
cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT,
MC_CMD_PRI_LOW, token);
cmd_flags,
token);