Commit e392b923 authored by Ian Campbell's avatar Ian Campbell Committed by Tom Rini

arndale: Apply Cortex-A15 errata #773022 and #774769

We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy

However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.

Searching around I found
which pointed towards
and CPU Errata 773022 and 774769.

This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.

The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no

Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.

I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.

Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.
Signed-off-by: default avatarIan Campbell <>
parent 9950098e
......@@ -681,8 +681,10 @@ The following options need to be configured:
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
......@@ -53,6 +53,20 @@ _secure_monitor:
bl psci_arch_init
#ifdef CONFIG_ARM_ERRATA_773022
mrc p15, 0, r5, c1, c0, 1
orr r5, r5, #(1 << 1)
mcr p15, 0, r5, c1, c0, 1
#ifdef CONFIG_ARM_ERRATA_774769
mrc p15, 0, r5, c1, c0, 1
orr r5, r5, #(1 << 25)
mcr p15, 0, r5, c1, c0, 1
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
......@@ -49,6 +49,10 @@
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
/* CPU Errata */
#define CONFIG_ARM_ERRATA_773022
#define CONFIG_ARM_ERRATA_774769
/* Power */
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