Commit e4430779 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nobuhiro Iwamatsu

sh: lowlevel_init coding style cleanup

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent 85cb052e
......@@ -33,17 +33,17 @@ lowlevel_init:
/*
* Set frequency multipliers and dividers in FRQCR.
*/
mov.l WTCSR_A,r1
mov.l WTCSR_D,r0
mov.w r0,@r1
mov.l WTCSR_A, r1
mov.l WTCSR_D, r0
mov.w r0, @r1
mov.l WTCNT_A,r1
mov.l WTCNT_D,r0
mov.w r0,@r1
mov.l WTCNT_A, r1
mov.l WTCNT_D, r0
mov.w r0, @r1
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.w r0, @r1
/*
* Setup CS0 (Flash).
......@@ -112,21 +112,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */
/*
* Spansion S29GL256N11 @ 48 MHz
*/
CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
/* 1 idle cycle inserted, normal space, 16 bit */
CS0BCR_D: .long 0x12490400
/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
CS0WCR_D: .long 0x00000340
/*
* Samsung K4S511632B-UL75 @ 48 MHz
* Micron MT48LC32M16A2-75 @ 48 MHz
*/
CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
SDCR_D2: .long 0x00000812 /* refresh */
RTCSR_D: .long 0xA55A0008 /* 1/4, once */
RTCNT_D: .long 0xA55A005D /* count 93 */
RTCOR_D: .long 0xa55a005d /* count 93 */
SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
CS3BCR_D: .long 0x10004400
/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
CS3WCR_D: .long 0x00000091
/* no refresh, 13 rows, 10 cols, NO bank active mode */
SDCR_D1: .long 0x00000012
SDCR_D2: .long 0x00000812 /* refresh */
RTCSR_D: .long 0xA55A0008 /* 1/4, once */
RTCNT_D: .long 0xA55A005D /* count 93 */
RTCOR_D: .long 0xa55a005d /* count 93 */
/* mode register CL2, burst read and SINGLE WRITE */
SDMR3_D: .long 0x440
/*
* Registers
......
......@@ -29,11 +29,11 @@
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
......@@ -203,7 +203,7 @@ bsc_init:
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
......@@ -232,28 +232,28 @@ MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
FRQCR_D: .long 0x07022538
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
.align 2
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
.align 2
PCCR_A: .long 0xa4050104
PCCR_D: .word 0x8800
PCCR_A: .long 0xa4050104
PCCR_D: .word 0x8800
.align 2
PECR_A: .long 0xa4050108
PECR_D: .word 0x0000
PECR_A: .long 0xa4050108
PECR_D: .word 0x0000
.align 2
PJCR_A: .long 0xa4050110
PJCR_D: .word 0x1000
PJCR_A: .long 0xa4050110
PJCR_D: .word 0x1000
.align 2
PXCR_A: .long 0xa4050148
PXCR_D: .word 0x0AAA
PXCR_A: .long 0xa4050148
PXCR_D: .word 0x0AAA
.align 2
CMNCR_A: .long CMNCR
......
......@@ -31,118 +31,118 @@
#include <asm/processor.h>
#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MARUBUN_PCCARD
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#else /* CONFIG_MARUBUN_PCCARD */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#endif /* CONFIG_MARUBUN_PCCARD */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#else /* CONFIG_CPU_SH7751 */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#endif /* CONFIG_CPU_SH7751 */
.global lowlevel_init
.text
.align 2
.align 2
lowlevel_init:
mov.l CCR_A, r1 ! CCR Address
mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1
mov.l CCR_A, r1 ! CCR Address
mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1
init_bsc:
mov.l FRQCR_A,r1 /* FRQCR Address */
mov.l FRQCR_D,r0 /* FRQCR Data */
mov.w r0,@r1
mov.l FRQCR_A, r1 /* FRQCR Address */
mov.l FRQCR_D, r0 /* FRQCR Data */
mov.w r0, @r1
mov.l BCR1_A,r1 /* BCR1 Address */
mov.l BCR1_D,r0 /* BCR1 Data */
mov.l r0,@r1
mov.l BCR1_A, r1 /* BCR1 Address */
mov.l BCR1_D, r0 /* BCR1 Data */
mov.l r0, @r1
mov.l BCR2_A,r1 /* BCR2 Address */
mov.l BCR2_D,r0 /* BCR2 Data */
mov.w r0,@r1
mov.l BCR2_A, r1 /* BCR2 Address */
mov.l BCR2_D, r0 /* BCR2 Data */
mov.w r0, @r1
mov.l WCR1_A,r1 /* WCR1 Address */
mov.l WCR1_D,r0 /* WCR1 Data */
mov.l r0,@r1
mov.l WCR1_A, r1 /* WCR1 Address */
mov.l WCR1_D, r0 /* WCR1 Data */
mov.l r0, @r1
mov.l WCR2_A,r1 /* WCR2 Address */
mov.l WCR2_D,r0 /* WCR2 Data */
mov.l r0,@r1
mov.l WCR2_A, r1 /* WCR2 Address */
mov.l WCR2_D, r0 /* WCR2 Data */
mov.l r0, @r1
mov.l WCR3_A,r1 /* WCR3 Address */
mov.l WCR3_D,r0 /* WCR3 Data */
mov.l r0,@r1
mov.l WCR3_A, r1 /* WCR3 Address */
mov.l WCR3_D, r0 /* WCR3 Data */
mov.l r0, @r1
mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D1,r0 /* MCR Data1 */
mov.l r0,@r1
mov.l MCR_A, r1 /* MCR Address */
mov.l MCR_D1, r0 /* MCR Data1 */
mov.l r0, @r1
mov.l SDMR3_A,r1 /* Set SDRAM mode */
mov #0,r0
mov.b r0,@r1
mov.l SDMR3_A, r1 /* Set SDRAM mode */
mov #0, r0
mov.b r0, @r1
! Do you need PCMCIA setting?
! If so, please add the lines here...
mov.l RTCNT_A,r1 /* RTCNT Address */
mov.l RTCNT_D,r0 /* RTCNT Data */
mov.w r0,@r1
mov.l RTCNT_A, r1 /* RTCNT Address */
mov.l RTCNT_D, r0 /* RTCNT Data */
mov.w r0, @r1
mov.l RTCOR_A,r1 /* RTCOR Address */
mov.l RTCOR_D,r0 /* RTCOR Data */
mov.w r0,@r1
mov.l RTCOR_A, r1 /* RTCOR Address */
mov.l RTCOR_D, r0 /* RTCOR Data */
mov.w r0, @r1
mov.l RTCSR_A,r1 /* RTCSR Address */
mov.l RTCSR_D,r0 /* RTCSR Data */
mov.w r0,@r1
mov.l RTCSR_A, r1 /* RTCSR Address */
mov.l RTCSR_D, r0 /* RTCSR Data */
mov.w r0, @r1
mov.l RFCR_A,r1 /* RFCR Address */
mov.l RFCR_D,r0 /* RFCR Data */
mov.w r0,@r1 /* Clear reflesh counter */
mov.l RFCR_A, r1 /* RFCR Address */
mov.l RFCR_D, r0 /* RFCR Data */
mov.w r0, @r1 /* Clear reflesh counter */
/* Wait DRAM refresh 30 times */
mov #30,r3
mov #30, r3
1:
mov.w @r1,r0
extu.w r0,r2
cmp/hi r3,r2
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D2,r0 /* MCR Data2 */
mov.l r0,@r1
mov.l MCR_A, r1 /* MCR Address */
mov.l MCR_D2, r0 /* MCR Data2 */
mov.l r0, @r1
mov.l SDMR3_A,r1 /* Set SDRAM mode */
mov #0,r0
mov.b r0,@r1
mov.l SDMR3_A, r1 /* Set SDRAM mode */
mov #0, r0
mov.b r0, @r1
rts
nop
nop
.align 2
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
FRQCR_A: .long FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R
......
......@@ -29,11 +29,11 @@
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
......@@ -176,7 +176,7 @@ bsc_init:
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
......
......@@ -39,111 +39,111 @@
lowlevel_init:
mov.l DRVCRA_A, r1
mov.l DRVCRA_D, r0
mov.l DRVCRA_D, r0
mov.w r0, @r1
mov.l DRVCRB_A, r1
mov.l DRVCRB_D, r0
mov.l DRVCRB_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1
mov.l RWTCSR_D1, r0
mov.l RWTCSR_D1, r0
mov.w r0, @r1
mov.l RWTCNT_A, r1
mov.l RWTCNT_D, r0
mov.l RWTCNT_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1
mov.l RWTCSR_D2, r0
mov.l RWTCSR_D2, r0
mov.w r0, @r1
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.l FRQCR_D, r0
mov.l r0, @r1
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
mov.l CS0BCR_A ,r1
mov.l CS0BCR_D ,r0
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
mov.l CS4BCR_A ,r1
mov.l CS4BCR_D ,r0
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
mov.l CS5ABCR_A ,r1
mov.l CS5ABCR_D ,r0
mov.l CS5ABCR_A, r1
mov.l CS5ABCR_D, r0
mov.l r0, @r1
mov.l CS5BBCR_A ,r1
mov.l CS5BBCR_D ,r0
mov.l CS5BBCR_A, r1
mov.l CS5BBCR_D, r0
mov.l r0, @r1
mov.l CS6ABCR_A ,r1
mov.l CS6ABCR_D ,r0
mov.l CS6ABCR_A, r1
mov.l CS6ABCR_D, r0
mov.l r0, @r1
mov.l CS6BBCR_A ,r1
mov.l CS6BBCR_D ,r0
mov.l CS6BBCR_A, r1
mov.l CS6BBCR_D, r0
mov.l r0, @r1
mov.l CS0WCR_A ,r1
mov.l CS0WCR_D ,r0
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
mov.l CS4WCR_A ,r1
mov.l CS4WCR_D ,r0
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
mov.l CS5AWCR_A ,r1
mov.l CS5AWCR_D ,r0
mov.l CS5AWCR_A, r1
mov.l CS5AWCR_D, r0
mov.l r0, @r1
mov.l CS5BWCR_A ,r1
mov.l CS5BWCR_D ,r0
mov.l CS5BWCR_A, r1
mov.l CS5BWCR_D, r0
mov.l r0, @r1
mov.l CS6AWCR_A ,r1
mov.l CS6AWCR_D ,r0
mov.l CS6AWCR_A, r1
mov.l CS6AWCR_D, r0
mov.l r0, @r1
mov.l CS6BWCR_A ,r1
mov.l CS6BWCR_D ,r0
mov.l CS6BWCR_A, r1
mov.l CS6BWCR_D, r0
mov.l r0, @r1
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D1, r0
mov.l SBSC_SDCR_D1, r0
mov.l r0, @r1
mov.l SBSC_SDWCR_A, r1
mov.l SBSC_SDWCR_D, r0
mov.l SBSC_SDWCR_D, r0
mov.l r0, @r1
mov.l SBSC_SDPCR_A, r1
mov.l SBSC_SDPCR_D, r0
mov.l SBSC_SDPCR_D, r0
mov.l r0, @r1
mov.l SBSC_RTCSR_A, r1
mov.l SBSC_RTCSR_D, r0
mov.l SBSC_RTCSR_D, r0
mov.l r0, @r1
mov.l SBSC_RTCNT_A, r1
mov.l SBSC_RTCNT_D, r0
mov.l SBSC_RTCNT_D, r0
mov.l r0, @r1
mov.l SBSC_RTCOR_A, r1
mov.l SBSC_RTCOR_D, r0
mov.l SBSC_RTCOR_D, r0
mov.l r0, @r1
mov.l SBSC_SDMR3_A1, r1
mov.l SBSC_SDMR3_D, r0
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SBSC_SDMR3_A2, r1
mov.l SBSC_SDMR3_D, r0
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SLEEP_CNT, r1
......@@ -153,18 +153,18 @@ lowlevel_init:
dt r1
mov.l SBSC_SDMR3_A3, r1
mov.l SBSC_SDMR3_D, r0
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D2, r0
mov.l SBSC_SDCR_D2, r0
mov.l r0, @r1
mov.l CCR_A, r1
mov.l CCR_D, r0
mov.l CCR_D, r0
mov.l r0, @r1
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
......@@ -211,7 +211,7 @@ SBSC_SDMR3_D: .long 0x00
CMNCR_A: .long CMNCR
CS0BCR_A: .long CS0BCR
CS4BCR_A: .long CS4BCR
CS5ABCR_A: .long CS5ABCR
CS5ABCR_A: .long CS5ABCR
CS5BBCR_A: .long CS5BBCR
CS6ABCR_A: .long CS6ABCR
CS6BBCR_A: .long CS6BBCR
......
......@@ -17,92 +17,92 @@ lowlevel_init:
mov.l CCR_A, r1
mov.l CCR_D_D, r0
mov.l r0,@r1
mov.l r0, @r1
mov.l MMUCR_A,r1
mov.l MMUCR_D,r0
mov.l r0,@r1
mov.l MMUCR_A, r1
mov.l MMUCR_D, r0
mov.l r0, @r1
mov.l BCR1_A,r1
mov.l BCR1_D,r0
mov.l r0,@r1
mov.l BCR1_A, r1
mov.l BCR1_D, r0
mov.l r0, @r1
mov.l BCR2_A,r1
mov.l BCR2_D,r0
mov.w r0,@r1
mov.l BCR2_A, r1
mov.l BCR2_D, r0
mov.w r0, @r1
mov.l BCR3_A,r1
mov.l BCR3_D,r0
mov.w r0,@r1
mov.l BCR3_A, r1
mov.l BCR3_D, r0
mov.w r0, @r1
mov.l BCR4_A,r1
mov.l BCR4_D,r0
mov.l r0,@r1
mov.l BCR4_A, r1
mov.l BCR4_D, r0
mov.l r0, @r1
mov.l WCR1_A,r1
mov.l WCR1_D,r0
mov.l r0,@r1
mov.l WCR1_A, r1
mov.l WCR1_D, r0
mov.l r0, @r1
mov.l WCR2_A,r1
mov.l WCR2_D,r0
mov.l r0,@r1
mov.l WCR2_A, r1
mov.l WCR2_D, r0
mov.l r0, @r1
mov.l WCR3_A,r1
mov.l WCR3_D,r0
mov.l r0,@r1
mov.l WCR3_A, r1
mov.l WCR3_D, r0
mov.l r0, @r1
mov.l PCR_A,r1
mov.l PCR_D,r0
mov.w r0,@r1
mov.l PCR_A, r1
mov.l PCR_D, r0
mov.w r0, @r1
mov.l LED_A,r1
mov #0xff,r0
mov.w r0,@r1
mov.l LED_A, r1
mov #0xff, r0
mov.w r0, @r1
mov.l MCR_A,r1
mov.l MCR_D1,r0
mov.l r0,@r1
mov.l MCR_A, r1
mov.l MCR_D1, r0
mov.l r0, @r1
mov.l RTCNT_A,r1
mov.l RTCNT_D,r0
mov.w r0,@r1
mov.l RTCNT_A, r1
mov.l RTCNT_D, r0
mov.w r0, @r1
mov.l RTCOR_A,r1
mov.l RTCOR_D,r0
mov.w r0,@r1
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.w r0, @r1
mov.l RFCR_A,r1
mov.l RFCR_D,r0
mov.w r0,@r1
mov.l RFCR_A, r1
mov.l RFCR_D, r0
mov.w r0, @r1
mov.l RTCSR_A,r1
mov.l RTCSR_D,r0
mov.w r0,@r1
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.w r0, @r1
mov.l SDMR3_A,r1
mov #0x55,r0
mov.b r0,@r1
mov.l SDMR3_A, r1
mov #0x55, r0
mov.b r0, @r1
/* Wait DRAM refresh 30 times */
mov.l RFCR_A,r1
mov #30,r3
mov.l RFCR_A, r1
mov #30, r3
1:
mov.w @r1,r0
extu.w r0,r2
cmp/hi r3,r2
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
mov.l MCR_A,r1
mov.l MCR_D2,r0
mov.l r0,@r1
mov.l MCR_A, r1
mov.l MCR_D2, r0
mov.l r0, @r1
mov.l SDMR3_A,r1
mov #0,r0
mov.b r0,@r1
mov.l SDMR3_A, r1
mov #0, r0
mov.b r0, @r1
mov.l IRLMASK_A,r1
mov.l IRLMASK_D,r0
mov.l r0,@r1
mov.l IRLMASK_A, r1
mov.l IRLMASK_D, r0
mov.l r0, @r1
mov.l CCR_A, r1
mov.l CCR_D_E, r0
......
This diff is collapsed.
......@@ -29,153 +29,153 @@
lowlevel_init:
/* Cache setting */
mov.l CCR1_A ,r1
mov.l CCR1_D ,r0
mov.l r0,@r1
mov.l CCR1_A, r1
mov.l CCR1_D, r0
mov.l r0, @r1