Commit ea8d989f authored by Timo Tuunainen's avatar Timo Tuunainen Committed by Peter Pearse

Support for Artila M-501 starter kit

Kimmo Leppala / Sysart and
Timo Tuunainen / Sysart
parent fe891ecf
......@@ -509,3 +509,19 @@ N: Nobuhiro Iwamatsu
E: iwamatsu@nigauri.org
D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
W: http://www.nigauri.org/~iwamatsu/
N: Alan Lu
E: alnalu001@gmail.com
D: Support for Artila M-501 starter kit
W: http://www.artila.com/
N: Kimmo Leppala
E: kimmo.leppala@sysart.fi
D: Support for Artila M-501 starter kit
W: http://www.sysart.fi/
N: Timo Tuunainen
E: timo.tuunainen@sysart.fi
D: Support for Artila M-501 starter kit
W: http://www.sysart.fi/
......@@ -459,6 +459,7 @@ LIST_ARM9=" \
cp946es \
cp966 \
lpd7a400 \
m501sk \
mp2usb \
mx1ads \
mx1fs2 \
......
......@@ -2308,6 +2308,8 @@ csb637_config : unconfig
mp2usb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
m501sk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t m501sk NULL at91rm9200
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
......
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := m501sk.o eeprom.o
SOBJS := memsetup.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################
TEXT_BASE = 0x21f00000
/*
* Add by Alan Lu, 07-29-2005
* For ATMEL AT24C16 EEPROM
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#ifdef CFG_EEPROM_AT24C16
#undef DEBUG
void eeprom_init(void)
{
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
#endif
}
int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
{
int page, count = 0, i = 0;
page = offset / 0x100;
i = offset % 0x100;
while (count < cnt) {
if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
return 1;
if (i > 0xff) {
page++;
i = 0;
}
}
return 0;
}
/*
* for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
*
* for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
* 0x00000nxx for EEPROM address selectors and page number at n.
*/
int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
{
int page, i = 0, count = 0;
page = offset / 0x100;
i = offset % 0x100;
while (count < cnt) {
if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0)
return 1;
if (i > 0xff) {
page++;
i = 0;
}
}
#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
return 0;
}
#ifndef CONFIG_SPI
int eeprom_probe(unsigned dev_addr, unsigned offset)
{
unsigned char chip;
/* Probe the chip address */
#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
chip = offset >> 8; /* block number */
#else
chip = offset >> 16; /* block number */
#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
chip |= dev_addr; /* insert device address */
return (i2c_probe(chip));
}
#endif
#endif
/*
* (C) Copyright 2008
* Based on modifications by Alan Lu / Artila
* Author : Timo Tuunainen / Sysart
Kimmo Leppala / Sysart
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
#include "m501sk.h"
#include "net.h"
#ifdef CONFIG_M501SK
void m501sk_gpio_init(void)
{
AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) |
1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) |
1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) |
1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96);
AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96);
AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96);
AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32);
AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32);
AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8);
/* Power OFF all USART's LEDs */
AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
AT91C_PA23_TXD2;
AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
AT91C_PA23_TXD2;
AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 |
AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
AT91C_PA23_TXD2;
AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1;
}
uchar m501sk_gpio_set(M501SK_PIO io)
{
uchar status = 0xff;
switch (io) {
case M501SK_DEBUG_LED1:
case M501SK_DEBUG_LED2:
case M501SK_DEBUG_LED3:
case M501SK_DEBUG_LED4:
case M501SK_READY_LED:
AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96);
status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
break;
case M501SK_BUZZER:
AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32);
status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
break;
}
return status;
}
uchar m501sk_gpio_clear(M501SK_PIO io)
{
uchar status = 0xff;
switch (io) {
case M501SK_DEBUG_LED1:
case M501SK_DEBUG_LED2:
case M501SK_DEBUG_LED3:
case M501SK_DEBUG_LED4:
case M501SK_READY_LED:
AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96);
status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96));
break;
case M501SK_BUZZER:
AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32);
status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32));
break;
}
return status;
}
void load_sernum_ethaddr(void)
{
return;
}
/*
* Miscelaneous platform dependent initialisations
*/
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* Correct IRDA resistor problem */
/* Set PA23_TXD in Output */
((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
gd->bd->bi_arch_number = MACH_TYPE_M501;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
m501sk_gpio_init();
/* Do interrupt init here, because flash needs timers */
interrupt_init();
flash_init();
return 0;
}
int dram_init(void)
{
int i = 0;
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
for (i = 0; i < 500; i++) {
m501sk_gpio_clear(M501SK_DEBUG_LED3);
m501sk_gpio_clear(M501SK_BUZZER);
udelay(250);
m501sk_gpio_set(M501SK_DEBUG_LED3);
m501sk_gpio_set(M501SK_BUZZER);
udelay(80);
}
m501sk_gpio_clear(M501SK_BUZZER);
m501sk_gpio_clear(M501SK_DEBUG_LED3);
return 0;
}
int board_late_init(void)
{
#if defined(CONFIG_CMD_NET)
eth_init(gd->bd);
eth_halt();
#endif
/* Protect U-Boot, kernel & ramdisk memory addresses */
run_command("protect on 10000000 1041ffff", 0);
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */
#endif /* CONFIG_M501SK */
This diff is collapsed.
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#ifdef CONFIG_BOOTBINFUNC
/*
* some parameters for the board
*
* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
* turn is based on the boot.bin code from ATMEL
*
*/
/* flash */
#define MC_PUIA 0xFFFFFF10
#define MC_PUIA_VAL 0x00000000
#define MC_PUP 0xFFFFFF50
#define MC_PUP_VAL 0x00000000
#define MC_PUER 0xFFFFFF54
#define MC_PUER_VAL 0x00000000
#define MC_ASR 0xFFFFFF04
#define MC_ASR_VAL 0x00000000
#define MC_AASR 0xFFFFFF08
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR 0xFFFFFF64
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR 0xFFFFFF70
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR 0xFFFFFC28
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
#define PLLBR 0xFFFFFC2C
#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR 0xFFFFFC30
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
#define MCKR_VAL 0x00000202
/* sdram */
#define PIOC_ASR 0xFFFFF870
#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
#define PIOC_BSR 0xFFFFF874
#define PIOC_BSR_VAL 0x00000000
#define PIOC_PDR 0xFFFFF804
#define PIOC_PDR_VAL 0xFFFF0000
#define EBI_CSA 0xFFFFFF60
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
#define SDRC_CR 0xFFFFFF98
#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
#define SDRAM 0x20000000 /* address of the SDRAM */
#define SDRAM1 0x20000080 /* address of the SDRAM */
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
#define SDRC_MR 0xFFFFFF90
#define SDRC_MR_VAL 0x00000002 /* Precharge All */
#define SDRC_MR_VAL1 0x00000004 /* refresh */
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR 0xFFFFFF94
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevelinit
lowlevelinit:
/* memory control configuration */
/* this isn't very elegant, but what the heck */
ldr r0, =SMRDATA
ldr r1, _TEXT_BASE
sub r0, r0, r1
add r2, r0, #80
0:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 0b
/* delay - this is all done by guess */
ldr r0, =0x00010000
1:
subs r0, r0, #1
bhi 1b
ldr r0, =SMRDATA1
ldr r1, _TEXT_BASE
sub r0, r0, r1
add r2, r0, #176
2:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 2b
/* everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.word MC_PUIA
.word MC_PUIA_VAL
.word MC_PUP
.word MC_PUP_VAL
.word MC_PUER
.word MC_PUER_VAL
.word MC_ASR
.word MC_ASR_VAL
.word MC_AASR
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
.word SMC2_CSR
.word SMC2_CSR_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR
.word PLLBR_VAL
.word MCKR
.word MCKR_VAL
/* SMRDATA is 80 bytes long */
/* here there's a delay of 100 */
SMRDATA1:
.word PIOC_ASR
.word PIOC_ASR_VAL
.word PIOC_BSR
.word PIOC_BSR_VAL
.word PIOC_PDR
.word PIOC_PDR_VAL
.word EBI_CSA
.word EBI_CSA_VAL
.word SDRC_CR
.word SDRC_CR_VAL
.word SDRC_MR
.word SDRC_MR_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRC_MR
.word SDRC_MR_VAL1
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRC_MR
.word SDRC_MR_VAL2
.word SDRAM1
.word SDRAM_VAL
.word SDRC_TR
.word SDRC_TR_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRC_MR
.word SDRC_MR_VAL3
.word SDRAM
.word SDRAM_VAL
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_BOOTBINFUNC */
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm920t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}
/*
* Based on Modifications by Alan Lu / Artila and
* Rick Bronson <rick@efn.org>
*
* Configuration settings for the Artila M-501 starter kit,
* with V02 processor card.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
/* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MAIN_CLOCK 179712000
/* Perip clock (AT91C_MASTER_CLOCK / 3) */
#define AT91C_MASTER_CLOCK 59904000
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#undef CONFIG_AUTOBOOT_PROMPT
#define CONFIG_MENUPROMPT "."
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
#define CFG_AT91C_BRGR_DIVISOR 33
/*
* Hardware drivers
*/
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_PROTECTION /*for Intel P30 Flash*/
#define CONFIG_HARD_I2C
#define CFG_I2C_SPEED 100
#define CFG_I2C_SLAVE 0
#define CFG_CONSOLE_INFO_QUIET
#undef CFG_ENV_IS_IN_EEPROM
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_AT24C16
#define CFG_I2C_RTC_ADDR 0x32
#undef CONFIG_RTC_DS1338
#define CONFIG_RTC_RS5C372A
#undef CONFIG_POST
#define CONFIG_M501SK
#define CONFIG_CMC_PU2
/* define one of these to choose the DBGU, USART0 or USART1 as console */
#define CONFIG_DBGU
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
"initrd=0x20800000,8192000 ramdisk_size=15360 " \
"root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
"128k(loader)ro,128k(reserved)ro,1408k(linux)" \
"ro,2560k(ramdisk)ro,-(userdisk)"
#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
#define CONFIG_BOOTDELAY 1