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Librem5
uboot-imx
Commits
eacbd317
Commit
eacbd317
authored
Jan 26, 2006
by
Zachary P. Landau
Browse files
Add support for Freescale M5271 processor
parent
c4b465f6
Changes
11
Hide whitespace changes
Inline
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CHANGELOG
View file @
eacbd317
...
...
@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add support for Freescale M5271 processor
Patch by Zachary Landau, 26 Jan 2006
* Fix 28F256J3A support on PM520 board
(without bank-switching only 32 MB can be accessed)
...
...
cpu/mcf52x2/cpu.c
View file @
eacbd317
...
...
@@ -25,6 +25,11 @@
#include
<watchdog.h>
#include
<command.h>
#ifdef CONFIG_M5271
#include
<asm/immap_5271.h>
#include
<asm/m5271.h>
#endif
#ifdef CONFIG_M5272
#include
<asm/immap_5272.h>
#include
<asm/m5272.h>
...
...
@@ -38,6 +43,41 @@
#include
<asm/m5249.h>
#endif
#ifdef CONFIG_M5271
int
checkcpu
(
void
)
{
puts
(
"CPU: MOTOROLA Coldfire MCF5271
\n
"
);
return
0
;
}
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
bd_t
*
bd
,
int
flag
,
int
argc
,
char
*
argv
[])
{
mbar_writeByte
(
MCF_RCM_RCR
,
MCF_RCM_RCR_SOFTRST
|
MCF_RCM_RCR_FRCRSTOUT
);
return
0
;
};
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset
(
void
)
{
mbar_writeShort
(
MCF_WTM_WSR
,
0x5555
);
mbar_writeShort
(
MCF_WTM_WSR
,
0xAAAA
);
}
int
watchdog_disable
(
void
)
{
mbar_writeShort
(
MCF_WTM_WCR
,
0
);
return
(
0
);
}
int
watchdog_init
(
void
)
{
mbar_writeShort
(
MCF_WTM_WCNTR
,
CONFIG_WATCHDOG_TIMEOUT
);
mbar_writeShort
(
MCF_WTM_WCR
,
MCF_WTM_WCR_EN
);
return
(
0
);
}
#endif
/* #ifdef CONFIG_WATCHDOG */
#endif
#ifdef CONFIG_M5272
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
bd_t
*
bd
,
int
flag
,
int
argc
,
char
*
argv
[])
{
...
...
cpu/mcf52x2/cpu_init.c
View file @
eacbd317
...
...
@@ -24,6 +24,11 @@
#include
<common.h>
#include
<watchdog.h>
#ifdef CONFIG_M5271
#include
<asm/m5271.h>
#include
<asm/immap_5271.h>
#endif
#ifdef CONFIG_M5272
#include
<asm/m5272.h>
#include
<asm/immap_5272.h>
...
...
@@ -38,6 +43,38 @@
#include
<asm/m5249.h>
#endif
#if defined(CONFIG_M5271)
void
cpu_init_f
(
void
)
{
#ifndef CONFIG_WATCHDOG
/* Disable the watchdog if we aren't using it */
mbar_writeShort
(
MCF_WTM_WCR
,
0
);
#endif
/* Set clockspeed to 100MHz */
mbar_writeShort
(
MCF_FMPLL_SYNCR
,
MCF_FMPLL_SYNCR_MFD
(
0
)
|
MCF_FMPLL_SYNCR_RFD
(
0
));
while
(
!
mbar_readByte
(
MCF_FMPLL_SYNSR
)
&
MCF_FMPLL_SYNSR_LOCK
);
/* Enable UART pins */
mbar_writeShort
(
MCF_GPIO_PAR_UART
,
MCF_GPIO_PAR_UART_U0TXD
|
MCF_GPIO_PAR_UART_U0RXD
|
MCF_GPIO_PAR_UART_U1RXD_UART1
|
MCF_GPIO_PAR_UART_U1TXD_UART1
);
/* Enable Ethernet pins */
mbar_writeByte
(
MCF_GPIO_PAR_FECI2C
,
CFG_FECI2C
);
}
/*
* initialize higher level parts of CPU like timers
*/
int
cpu_init_r
(
void
)
{
return
(
0
);
}
#endif
#if defined(CONFIG_M5272)
/*
* Breath some life into the CPU...
...
...
cpu/mcf52x2/fec.c
View file @
eacbd317
...
...
@@ -25,6 +25,11 @@
#include
<malloc.h>
#include
<asm/fec.h>
#ifdef CONFIG_M5271
#include
<asm/m5271.h>
#include
<asm/immap_5271.h>
#endif
#ifdef CONFIG_M5272
#include
<asm/m5272.h>
#include
<asm/immap_5272.h>
...
...
@@ -41,7 +46,7 @@
#ifdef CONFIG_M5272
#define FEC_ADDR (CFG_MBAR + 0x840)
#endif
#ifdef
CONFIG_M5282
#if
def
ined(
CONFIG_M5282
) || defined(CONFIG_M5271)
#define FEC_ADDR (CFG_MBAR + 0x1000)
#endif
...
...
@@ -240,10 +245,22 @@ int eth_init (bd_t * bd)
#endif
#undef ea
#ifdef CONFIG_M5271
/* Clear multicast address hash table
*/
fecp
->
fec_ghash_table_high
=
0
;
fecp
->
fec_ghash_table_low
=
0
;
/* Clear individual address hash table
*/
fecp
->
fec_ihash_table_high
=
0
;
fecp
->
fec_ihash_table_low
=
0
;
#else
/* Clear multicast address hash table
*/
fecp
->
fec_hash_table_high
=
0
;
fecp
->
fec_hash_table_low
=
0
;
#endif
/* Set maximum receive buffer size.
*/
...
...
@@ -295,6 +312,9 @@ int eth_init (bd_t * bd)
fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
#else
/* Half duplex mode */
fecp
->
fec_r_cntrl
=
FEC_RCNTRL_MII_MODE
|
FEC_RCNTRL_DRT
;
#ifdef CONFIG_M5271
fecp
->
fec_r_cntrl
|=
(
PKT_MAXBUF_SIZE
<<
16
);
/* set max frame length */
#endif
fecp
->
fec_x_cntrl
=
0
;
#endif
/* Set MII speed */
...
...
cpu/mcf52x2/interrupts.c
View file @
eacbd317
...
...
@@ -27,6 +27,11 @@
#include
<watchdog.h>
#include
<asm/processor.h>
#ifdef CONFIG_M5271
#include
<asm/m5271.h>
#include
<asm/immap_5271.h>
#endif
#ifdef CONFIG_M5272
#include
<asm/m5272.h>
#include
<asm/immap_5272.h>
...
...
@@ -171,7 +176,7 @@ int interrupt_init (void)
}
#endif
#ifdef
CONFIG_M5282
#if
def
ined(
CONFIG_M5282
) || defined(CONFIG_M5271)
int
interrupt_init
(
void
)
{
return
0
;
...
...
cpu/mcf52x2/serial.c
View file @
eacbd317
...
...
@@ -26,6 +26,10 @@
#include
<asm/mcfuart.h>
#ifdef CONFIG_M5271
#include
<asm/m5271.h>
#endif
#ifdef CONFIG_M5272
#include
<asm/m5272.h>
#endif
...
...
@@ -46,7 +50,7 @@
void
rs_serial_setbaudrate
(
int
port
,
int
baudrate
)
{
#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
|| defined(CONFIG_M5271)
volatile
unsigned
char
*
uartp
;
double
clock
,
fraction
;
...
...
@@ -61,8 +65,10 @@ void rs_serial_setbaudrate(int port,int baudrate)
uartp
[
MCFUART_UBG1
]
=
(((
int
)
clock
>>
8
)
&
0xff
);
/* set msb baud */
uartp
[
MCFUART_UBG2
]
=
((
int
)
clock
&
0xff
);
/* set lsb baud */
#ifndef CONFIG_M5271
uartp
[
MCFUART_UFPD
]
=
((
int
)
fraction
&
0xf
);
/* set baud fraction adjust */
#endif
#endif
};
void
rs_serial_init
(
int
port
,
int
baudrate
)
...
...
cpu/mcf52x2/start.S
View file @
eacbd317
...
...
@@ -55,7 +55,11 @@
*/
_vectors
:
#ifndef CONFIG_M5271
.
long
0
x00000000
,
_START
#else
.
long
0
x00000000
,
0x400
/*
Flash
offset
is
0
until
we
setup
CS0
*/
#endif
.
long
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
.
long
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
.
long
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
,
_FAULT
...
...
@@ -124,26 +128,42 @@ _start:
movec
%
d0
,
%
RAMBAR0
#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
#ifdef
CONFIG_M5282
#if
def
ined(
CONFIG_M5282
) || defined(CONFIG_M5271)
/
*
Initialize
IPSBAR
*/
move.l
#(
CFG_MBAR
+
1
),
%
d0
/*
set
IPSBAR
address
+
valid
flag
*/
move.l
%
d0
,
0x40000000
#ifdef CONFIG_M5282
/
*
Initialize
FLASHBAR
:
locate
internal
Flash
and
validate
it
*/
move.l
#(
CFG_INT_FLASH_BASE
+
0x21
),
%
d0
movec
%
d0
,
%
RAMBAR0
#endif
/
*
Initialize
RAMBAR1
:
locate
SRAM
and
validate
it
*/
move.l
#(
CFG_INIT_RAM_ADDR
+
0x21
),
%
d0
movec
%
d0
,
%
RAMBAR1
#ifdef CONFIG_M5271
move.l
#(
_flash_setup
-
CFG_FLASH_BASE
),
%a0
move.l
#(
_flash_setup_end
-
CFG_FLASH_BASE
),
%a1
move.l
#(
CFG_INIT_RAM_ADDR
),
%a2
_copy_flash
:
move.l
(
%a0
)+,
(
%a2
)+
cmp.l
%a0
,
%a1
bgt.s
_copy_flash
#endif
jmp
CFG_INIT_RAM_ADDR
_after_flash_copy
:
#endif
#if 0
/
*
invalidate
and
disable
cache
*/
move.l
#
0x01000000
,
%
d0
/*
Invalidate
cache
cmd
*/
movec
%
d0
,
%
CACR
/*
Invalidate
cache
*/
move.l
#
0
,
%
d0
movec
%
d0
,
%
ACR0
movec
%
d0
,
%
ACR1
#endif
/
*
set
stackpointer
to
end
of
internal
ram
to
get
some
stackspace
for
the
first
c
-
code
*/
move.l
#(
CFG_INIT_RAM_ADDR
+
CFG_INIT_SP_OFFSET
),
%
sp
...
...
@@ -158,6 +178,18 @@ _start:
/*------------------------------------------------------------------------------*/
#ifdef CONFIG_M5271
_flash_setup
:
move.l
#
0x1000
,
%
d0
move.w
%
d0
,
0x40000080
move.l
#
0x2180
,
%
d0
move.w
%
d0
,
0x4000008A
move.l
#
0x3f0001
,
%
d0
move.l
%
d0
,
0x40000084
jmp
_after_flash_copy
.
L
_flash_setup_end
:
#endif
/*
*
void
relocate_code
(
addr_sp
,
gd
,
addr_moni
)
*
...
...
include/asm-m68k/mcftimer.h
View file @
eacbd317
...
...
@@ -45,7 +45,7 @@
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define MCFTIMER_BASE1 0x140
/* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x180
/* Base address of TIMER2 */
#elif defined(CONFIG_M5282)
#elif defined(CONFIG_M5282)
| defined(CONFIG_M5271)
#define MCFTIMER_BASE1 0x150000
/* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x160000
/* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x170000
/* Base address of TIMER4 */
...
...
include/asm-m68k/mcfuart.h
View file @
eacbd317
...
...
@@ -46,7 +46,7 @@
#define MCFUART_BASE1 0x140
/* Base address of UART1 */
#define MCFUART_BASE2 0x180
/* Base address of UART2 */
#endif
#elif defined(CONFIG_M5282)
#elif defined(CONFIG_M5282)
|| defined(CONFIG_M5271)
#define MCFUART_BASE1 0x200
/* Base address of UART1 */
#define MCFUART_BASE2 0x240
/* Base address of UART2 */
#define MCFUART_BASE3 0x280
/* Base address of UART3 */
...
...
include/asm-m68k/ptrace.h
View file @
eacbd317
...
...
@@ -43,7 +43,7 @@ struct pt_regs {
ulong
a4
;
ulong
a5
;
ulong
a6
;
#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249)
#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249)
|| defined(CONFIG_M5271)
unsigned
format
:
4
;
/* frame format specifier */
unsigned
vector
:
12
;
/* vector offset */
unsigned
short
sr
;
...
...
lib_m68k/time.c
View file @
eacbd317
...
...
@@ -27,6 +27,11 @@
#include
<asm/mcftimer.h>
#ifdef CONFIG_M5271
#include
<asm/m5271.h>
#include
<asm/immap_5271.h>
#endif
#ifdef CONFIG_M5272
#include
<asm/m5272.h>
#include
<asm/immap_5272.h>
...
...
@@ -43,7 +48,7 @@
static
ulong
timestamp
;
#ifdef
CONFIG_M5282
#if
def
ined(
CONFIG_M5282
) || defined(CONFIG_M5271)
static
unsigned
short
lastinc
;
#endif
...
...
@@ -127,7 +132,7 @@ void set_timer (ulong t)
}
#endif
#if defined(CONFIG_M5282)
#if defined(CONFIG_M5282)
|| defined(CONFIG_M5271)
void
udelay
(
unsigned
long
usec
)
{
...
...
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