Commit ec0cc98f authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

parents 032c6867 db4a1767
......@@ -57,7 +57,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_USB_LIODN(1, "fsl-usb2-dr", 553),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
......
......@@ -424,7 +424,6 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
ulong flag = 0;
extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
......@@ -499,18 +498,11 @@ ulong cpu_init_f(void)
in_be32(&gur->dcsrcr);
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
return flag;
return 0;
}
/* Implement a dummy function for those platforms w/o SERDES */
......
......@@ -15,16 +15,16 @@
#include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1
static u64 serdes1_prtcl_map;
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
static u64 serdes2_prtcl_map;
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
static u64 serdes3_prtcl_map;
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
static u64 serdes4_prtcl_map;
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef DEBUG
......@@ -78,24 +78,30 @@ static const char *serdes_prtcl_str[] = {
[INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B",
[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
};
#endif
int is_serdes_configured(enum srds_prtcl device)
{
u64 ret = 0;
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
ret |= (1ULL << device) & serdes1_prtcl_map;
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
ret |= (1ULL << device) & serdes2_prtcl_map;
ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
ret |= (1ULL << device) & serdes3_prtcl_map;
ret |= serdes3_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
ret |= (1ULL << device) & serdes4_prtcl_map;
ret |= serdes4_prtcl_map[device];
#endif
return !!ret;
......@@ -171,12 +177,14 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
#define BCAP_OVD_MASK 0x10000000
#define BYP_CAL_MASK 0x02000000
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
......@@ -312,38 +320,43 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
serdes_prtcl_map |= (1ULL << lane_prtcl);
if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
else
serdes_prtcl_map[lane_prtcl] = 1;
}
return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
serdes_init(FSL_SRDS_3,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
serdes_init(FSL_SRDS_4,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);
#endif
}
......
......@@ -11,6 +11,7 @@
static u8 serdes_cfg_tbl[][4] = {
[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
......@@ -20,6 +21,7 @@ static u8 serdes_cfg_tbl[][4] = {
[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
......
......@@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
......
......@@ -15,6 +15,7 @@
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <vsc9953.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -271,5 +272,9 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif
#ifdef CONFIG_VSC9953
vsc9953_init(bis);
#endif
return 0;
}
/*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Dummy header file to enable CONFIG_OF_CONTROL.
* If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
* It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
* OF_CONTROL must have arch/gpio.h.
*/
#ifndef __ASM_ARCH_MX85XX_GPIO_H
#define __ASM_ARCH_MX85XX_GPIO_H
#endif
......@@ -12,6 +12,8 @@
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
#elif defined(CONFIG_C29XPCIE)
#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
......
......@@ -87,6 +87,13 @@ enum srds_prtcl {
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
SGMII_SW1_MAC1,
SGMII_SW1_MAC2,
SGMII_SW1_MAC3,
SGMII_SW1_MAC4,
SGMII_SW1_MAC5,
SGMII_SW1_MAC6,
SERDES_PRCTL_COUNT /* Keep this item the last one */
};
enum srds {
......
......@@ -346,13 +346,6 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
#ifdef CONFIG_DEEP_SLEEP
const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
u32 start_addr;
typedef void (*func_t)(void);
func_t kernel_resume;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
......@@ -372,20 +365,6 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
#ifdef CONFIG_DEEP_SLEEP
/* Jump to kernel in deep sleep case */
if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif
enable_cpc();
start_addr = in_be32(&scfg->sparecr[1]);
kernel_resume = (func_t)start_addr;
kernel_resume();
}
#endif
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
......
......@@ -6,3 +6,5 @@ F: include/configs/C29XPCIE.h
F: configs/C29XPCIE_defconfig
F: configs/C29XPCIE_NAND_defconfig
F: configs/C29XPCIE_SPIFLASH_defconfig
F: configs/C29XPCIE_NOR_SECBOOT_defconfig
F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
......@@ -27,3 +27,4 @@ F: configs/P5040DS_defconfig
F: configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig
F: configs/P5040DS_SECURE_BOOT_defconfig
......@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -152,6 +153,19 @@ found:
#endif
}
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *qixis_base = (void *)QIXIS_BASE;
/* does not provide HW signals for power management */
clrbits_8(qixis_base + 0x21, 0x2);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
......@@ -166,5 +180,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size;
}
......@@ -19,10 +19,10 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
}
int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0;
}
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
......@@ -395,14 +405,3 @@ void qixis_dump_switch(void)
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
......@@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
#define CPLD_PCIE_SGMII_MUX 0x80
#define CPLD_OVERRIDE_BOOT_EN 0x01
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
......@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -136,6 +137,19 @@ found:
#endif
}
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
/* does not provide HW signals for power management */
clrbits_8(cpld_base + 0x17, 0x40);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
......@@ -150,5 +164,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size;
}
......@@ -21,6 +21,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/fman.h"
int board_eth_init(bd_t *bis)
{
......@@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
/* Set the on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0x95:
/* 10G XFI with Aquantia PHY */
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
/* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
case 0x77:
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
srds_s1);
......@@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII_2500:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
......@@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop(fdt, offset, "phy-connection-type",
"sgmii-2500", 10);
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
}
void fdt_fixup_board_enet(void *fdt)
{
}
......@@ -11,6 +11,7 @@
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -42,6 +43,12 @@ void board_init_f(ulong bootflag)
console_init_f();
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (is_warm_boot())
fsl_dp_disable_console();
#endif
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
......
......@@ -16,10 +16,10 @@
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <asm/mpc85xx_gpio.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#include "cpld.h"
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -27,6 +27,11 @@ int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
......@@ -50,7 +55,40 @@ int checkboard(void)
#endif
puts("SERDES Reference Clocks:\n");
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
if (srds_s1 == 0x95)
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
else
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
return 0;
}
static void board_mux_lane(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
u8 reg = CPLD_READ(misc_ctl_status);
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
if (srds_prtcl_s1 == 0x95) {
/* Route Lane B to PCIE */
CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
} else {
/* Route Lane B to SGMII */
CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
}
CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
}
int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0;
}
......@@ -86,6 +124,7 @@ int board_early_init_r(void)
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
board_mux_lane();
return 0;
}
......@@ -131,14 +170,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
......@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -100,6 +101,19 @@ found:
#endif
}
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *qixis_base = (void *)QIXIS_BASE;
/* does not provide HW signals for power management */
clrbits_8(qixis_base + 0x21, 0x2);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
......@@ -112,5 +126,10 @@ phys_size_t initdram(int board_type)
dram_size *= 0x100000;
puts(" DDR: ");
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size;
}
......@@ -18,6 +18,7 @@
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
#include <vsc9953.h>
#include "../common/fman.h"
#include "../common/qixis.h"
......@@ -216,6 +217,7 @@ static void initialize_lane_to_slot(void)
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
lane_to_slot[6] = 7;
lane_to_slot[7] = 7;
break;
case 0x8d:
......@@ -438,6 +440,12 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
#ifdef CONFIG_VSC9953
int lane;
int phy_addr;
phy_interface_t phy_int;
struct mii_dev *bus;
#endif
printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk();
......@@ -477,6 +485,7 @@ int board_eth_init(bd_t *bis)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_mdio(i, NULL);
break;
case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i);
......@@ -491,6 +500,90 @@ int board_eth_init(bd_t *bis)
}
}
#ifdef CONFIG_VSC9953
for (i = 0; i < VSC9953_MAX_PORTS; i++) {
lane = -1;
phy_addr = 0;
phy_int = PHY_INTERFACE_MODE_NONE;
switch (i) {
case 0:
case 1:
case 2:
case 3:
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
/* PHYs connected over QSGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
break;
}
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_SW1_MAC1 + i);
if (lane < 0)