Commit ec497ffb authored by Angus Ainslie (Purism)'s avatar Angus Ainslie (Purism)
Browse files

enable the gpios


Signed-off-by: default avatarAngus Ainslie (Purism) <angus@akkea.ca>
parent 11a4c31c
......@@ -46,7 +46,23 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx8m-som {
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x3f
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x3f
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0xC0
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0xC0
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x3f
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x3f
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x3f
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x3f
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x3f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000003f
......
......@@ -101,8 +101,6 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
#define PAD_CTL_FSEL3 (0x3 << 3)
#define PAD_CTL_FSEL4 (0x4 << 3)
#define PAD_CTL_FSEL5 (0x5 << 3)
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#define PAD_CTL_ODE (0x1 << 5)
#define PAD_CTL_PUE (0x1 << 6)
......
......@@ -38,7 +38,7 @@ void spl_dram_init(void)
ddr_init(&dram_timing_b0);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE7 | PAD_CTL_SPEED_MAX)
#define I2C_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | PAD_CTL_FSEL3)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
......@@ -113,7 +113,7 @@ int board_mmc_getcd(struct mmc *mmc)
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL0)
PAD_CTL_FSEL1)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
......@@ -284,6 +284,42 @@ out:
}
#endif
/* not configured yet */
#define NFC_EN IMX_GPIO_NR(4, 28)
#define WWAN_EN IMX_GPIO_NR(3, 18)
#define GPS_EN IMX_GPIO_NR(3, 12)
#define WIFI_EN IMX_GPIO_NR(3, 10)
#define SMC_EN IMX_GPIO_NR(1, 6)
#define DSI_EN IMX_GPIO_NR(1, 5)
#define DSI_BIAS_EN IMX_GPIO_NR(1, 20)
#define CAMERA_EN IMX_GPIO_NR(1, 0)
#define FLASH_EN IMX_GPIO_NR(1, 23)
#define WWAN_nRESET IMX_GPIO_NR(3, 1)
#define BL_EN IMX_GPIO_NR(3, 14)
/* configured */
#define SD_EN IMX_GPIO_NR(1, 3)
#define AUDIO_EN IMX_GPIO_NR(1, 4)
#define VOL_UP IMX_GPIO_NR(1, 6)
#define VOL_DOWN IMX_GPIO_NR(1, 7)
#define TYPEC_MUX_EN IMX_GPIO_NR(1, 11)
#define HUB_nRESET IMX_GPIO_NR(1, 12)
#define HUB_EN IMX_GPIO_NR(1, 14)
#define CHG_EN IMX_GPIO_NR(3, 2)
#define CHG_OTG_OUT_EN IMX_GPIO_NR(3, 4)
static iomux_v3_cfg_t const configure_pads[] = {
IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(PAD_CTL_PUE),
IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(PAD_CTL_PUE),
IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6),
};
void spl_board_init(void)
{
#ifndef CONFIG_SPL_USB_SDP_SUPPORT
......@@ -375,5 +411,16 @@ void board_init_f(ulong dummy)
sdp_mmc_init();
}
imx_iomux_v3_setup_multiple_pads(configure_pads, ARRAY_SIZE(configure_pads));
gpio_direction_input(VOL_UP);
gpio_direction_input(VOL_DOWN);
gpio_direction_output(TYPEC_MUX_EN, 1);
gpio_direction_output(CHG_EN, 1);
gpio_direction_output(CHG_OTG_OUT_EN, 1);
gpio_direction_output(HUB_EN, 1);
gpio_direction_output(HUB_nRESET, 1);
gpio_direction_output(SD_EN, 1);
gpio_direction_output(AUDIO_EN, 1);
board_init_r(NULL, 0);
}
......@@ -47,7 +47,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y
CONFIG_NXP_TMU=y
CONFIG_USB=y
#CONFIG_DM_USB=y
CONFIG_DM_USB=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
......@@ -78,8 +78,8 @@ CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_USB_XHCI_IMX8M=y
CONFIG_USB_XHCI_DWC3=y
#CONFIG_USB_EHCI_HCD=y
#CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
......
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