Commit ed9e4e42 authored by York Sun's avatar York Sun
Browse files

mpc85xx/t208xqds: Adjust DDR timing parameters



Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of
1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in
case such DIMM comes available.

Also update single-rank 1866 timing. Enable interactive debugging as well.
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
parent 2519cb34
......@@ -28,17 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
{2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
{2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
{2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
{2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
{2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
{1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
{1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
......
......@@ -234,7 +234,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
......
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