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Commit efe2a4d5 authored by wdenk's avatar wdenk
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Code cleanup.

parent bea8e84b
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README
View file @ efe2a4d5
......@@ -835,7 +835,7 @@ The following options need to be configured:
function struct part_info* jffs2_part_info(int part_num)
If you define only one JFFS2 partition you may also want to
#define CFG_JFFS_SINGLE_PART 1
#define CFG_JFFS_SINGLE_PART 1
to disable the command chpart. This is the default when you
have not defined a custom partition
......@@ -1978,7 +1978,7 @@ Low Level (hardware related) configuration options:
initializations.
- CFG_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx/82xx systems only]
- CFG_INIT_RAM_ADDR:
......@@ -2118,13 +2118,13 @@ Low Level (hardware related) configuration options:
"md/mw" commands.
Examples:
=> mdc.b 10 4 500
=> mdc.b 10 4 500
This command will print 4 bytes (10,11,12,13) each 500 ms.
=> mwc.l 100 12345678 10
=> mwc.l 100 12345678 10
This command will write 12345678 to address 100 all 10 ms.
This only takes effect if the memory commands are activated
This only takes effect if the memory commands are activated
globally (CFG_CMD_MEM).
Building the Software:
......
board/esd/apc405/strataflash.c
View file @ efe2a4d5
......@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/processor.h>
#undef DEBUG_FLASH
#undef DEBUG_FLASH
/*
* This file implements a Common Flash Interface (CFI) driver for ppcboot.
* The width of the port and the width of the chips are determined at initialization.
......@@ -85,12 +85,8 @@
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
#define FLASH_MAN_CFI 0x01000000
typedef union {
unsigned char c;
unsigned short w;
......@@ -107,13 +103,10 @@ typedef union {
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
......@@ -249,7 +242,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
rcode = 1;
} else
......@@ -277,7 +270,7 @@ void flash_print_info (flash_info_t *info)
info->size >> 20, info->sector_count);
printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
#ifdef CFG_FLASH_EMPTY_INFO
......@@ -286,28 +279,28 @@ void flash_print_info (flash_info_t *info)
int erased;
volatile unsigned long *flash;
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++)
{
if (*flash++ != 0xffffffff)
{
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
/* print empty and read-only info */
/* print empty and read-only info */
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
......@@ -414,7 +407,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot)
else
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
prot?"protect":"unprotect")) == 0) {
info->protect[sector] = prot;
......@@ -464,7 +457,7 @@ static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout
printf("Command Sequence Error.\n");
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
printf("Block Erase Error.\n");
retcode = ERR_NOT_ERASED;
retcode = ERR_NOT_ERASED;
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
printf("Locking Error\n");
}
......@@ -733,7 +726,7 @@ static int find_sector(flash_info_t *info, ulong addr)
{
int sector;
for(sector = info->sector_count - 1; sector >= 0; sector--) {
if(addr >= info->start[sector])
if(addr >= info->start[sector])
break;
}
return sector;
......@@ -741,7 +734,7 @@ static int find_sector(flash_info_t *info, ulong addr)
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
{
int sector;
int cnt;
int retcode;
......@@ -789,8 +782,8 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, in
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
"buffer write");
}
}
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
}
}
#endif /* CFG_USE_FLASH_BUFFER_WRITE */
board/esd/common/lcd.c
View file @ efe2a4d5
......@@ -136,7 +136,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
}
s1dValue = regs[i].Value;
lcd_reg[s1dReg] = s1dValue;
}
}
/*
* Decompress bmp image
......
board/esd/common/lcd.h
View file @ efe2a4d5
......@@ -68,4 +68,3 @@ typedef struct /**** BMP file info structure ****/
unsigned int biClrUsed; /* Number of colors used */
unsigned int biClrImportant; /* Number of important colors */
} BITMAPINFOHEADER;
board/esd/common/s1d13806_1024_768_8bpp.h
View file @ efe2a4d5
......@@ -123,4 +123,3 @@ static S1D_REGS regs_13806_1024_768_8bpp[] =
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
{0x01FC,0x01}, /* Display Mode Register */
};
board/esd/common/s1d13806_320_240_4bpp.h
View file @ efe2a4d5
......@@ -123,4 +123,3 @@ static S1D_REGS regs_13806_320_240_4bpp[] =
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
{0x01FC,0x01}, /* Display Mode Register */
};
board/esd/common/s1d13806_640_480_16bpp.h
View file @ efe2a4d5
......@@ -123,4 +123,3 @@ static S1D_REGS regs_13806_640_480_16bpp[] =
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
{0x01FC,0x01}, /* Display Mode Register */
};
board/esd/common/s1d13806_640_480_8bpp.h
View file @ efe2a4d5
......@@ -123,4 +123,3 @@ static S1D_REGS regs_13806_640_320_16bpp[] =
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
{0x01FC,0x01}, /* Display Mode Register */
};
board/esd/cpci405/cpci405.c
View file @ efe2a4d5
......@@ -559,11 +559,11 @@ void ide_set_reset(int on)
#ifdef CONFIG_CPCI405AB
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|= CFG_FPGA_MODE_1WIRE_DIR)
|= CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
&= ~CFG_FPGA_MODE_1WIRE_DIR)
&= ~CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
& CFG_FPGA_MODE_1WIRE)
& CFG_FPGA_MODE_1WIRE)
/*
* Generate a 1-wire reset, return 1 if no presence detect was found,
......
board/esd/cpci750/i2c.c
View file @ efe2a4d5
......@@ -72,28 +72,28 @@ static void i2c_init (int speed, int slaveaddr)
/* Setup bus */
/* gtI2cReset */
GT_REG_WRITE (I2C_SOFT_RESET, 0);
asm(" sync");
asm(" sync");
GT_REG_WRITE (I2C_CONTROL, 0);
asm(" sync");
asm(" sync");
DP (puts ("set baudrate\n"));
GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
asm(" sync");
asm(" sync");
DP (puts ("udelay...\n"));
udelay (I2C_DELAY);
GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
asm(" sync");
asm(" sync");
}
static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
{
unsigned int status, data, bits = 7;
unsigned int control;
unsigned int control;
int count = 0;
DP (puts ("i2c_select_device\n"));
......@@ -107,19 +107,19 @@ static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
GT_REG_READ (I2C_CONTROL, &control);
control |= (0x1 << 2);
GT_REG_WRITE (I2C_CONTROL, control);
asm(" sync");
asm(" sync");
GT_REG_READ (I2C_CONTROL, &control);
control |= (0x1 << 5); /* generate the I2C_START_BIT */
GT_REG_WRITE (I2C_CONTROL, control);
asm(" sync");
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
asm(" sync");
asm(" sync");
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_CONTROL, &status);
}
count = 0;
......@@ -128,7 +128,7 @@ static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
if (count > 200) {
#ifdef DEBUG_I2C
printf ("Failed to set startbit: 0x%02x\n", status);
printf ("Failed to set startbit: 0x%02x\n", status);
#endif
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
asm(" sync");
......@@ -146,21 +146,21 @@ static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
/* set the read bit */
data |= read;
GT_REG_WRITE (I2C_DATA, data);
asm(" sync");
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, BIT3);
asm(" sync");
asm(" sync");
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count = 0;
while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
if (count > 200) {
#ifdef DEBUG_I2C
printf ("Failed to write address: 0x%02x\n", status);
printf ("Failed to write address: 0x%02x\n", status);
#endif
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
......@@ -195,15 +195,15 @@ static uchar i2c_get_data (uchar * return_data, int len)
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x50) {
if (count > 20) {
#ifdef DEBUG_I2C
printf ("Failed to get data len status: 0x%02x\n", status);
printf ("Failed to get data len status: 0x%02x\n", status);
#endif
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
asm(" sync");
......@@ -219,13 +219,13 @@ static uchar i2c_get_data (uchar * return_data, int len)
}
RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
asm(" sync");
asm(" sync");
count = 0;
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
GT_REG_READ (I2C_CONTROL, &status);
}
while ((status & 0xff) != 0x58) {
if (count > 2000) {
......@@ -236,9 +236,9 @@ static uchar i2c_get_data (uchar * return_data, int len)
count++;
}
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
asm(" sync");
asm(" sync");
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
asm(" sync");
asm(" sync");
return (0);
}
......@@ -254,7 +254,7 @@ static uchar i2c_write_data (unsigned int *data, int len)
DP (puts ("i2c_write_data\n"));
while (len) {
count = 0;
count = 0;
temp = (unsigned int) (*temp_ptr);
GT_REG_WRITE (I2C_DATA, temp);
asm(" sync");
......@@ -264,7 +264,7 @@ static uchar i2c_write_data (unsigned int *data, int len)
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
......@@ -294,7 +294,7 @@ static uchar i2c_write_byte (unsigned char *data, int len)
DP (puts ("i2c_write_byte\n"));
while (len) {
count = 0;
count = 0;
/* Set and assert the data */
temp = *temp_ptr;
GT_REG_WRITE (I2C_DATA, temp);
......@@ -306,7 +306,7 @@ static uchar i2c_write_byte (unsigned char *data, int len)
GT_REG_READ (I2C_CONTROL, &status);
while ((status & 0x08) != 0x08) {
GT_REG_READ (I2C_CONTROL, &status);
}
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
......@@ -419,7 +419,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
void i2c_stop (void)
{
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
asm(" sync");
asm(" sync");
}
......@@ -441,7 +441,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
status);
#endif
return status;
}
}
status = i2c_write_byte (data, len); /* write the data */
......@@ -450,7 +450,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
printf ("Data not written: 0x%02x\n", status);
#endif
return status;
}
}
/* issue a stop bit */
i2c_stop ();
return 0;
......
board/esd/cpci750/ide.c
View file @ efe2a4d5
......@@ -32,41 +32,34 @@
extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
int ide_preinit
(
void
)
{
int status;
pci_dev_t devbusfn;
int l;
int ide_preinit (void)
{
int status;
pci_dev_t devbusfn;
int l;
status = 1;
for(l=0;l<CFG_IDE_MAXBUS;l++)
{
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device(0x1103, 0x0004, 0);
if (devbusfn != -1)
{
status = 0;
status = 1;
for (l = 0; l < CFG_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
if (devbusfn != -1) {
status = 0;
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&ide_bus_offset[0]);
ide_bus_offset[0] &= 0xfffffffe;
ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, (u32 *)&ide_bus_offset[1]);
ide_bus_offset[1] &= 0xfffffffe;
ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
}
return(status);
}
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
(u32 *) & ide_bus_offset[0]);
ide_bus_offset[0] &= 0xfffffffe;
ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
(u32 *) & ide_bus_offset[1]);
ide_bus_offset[1] &= 0xfffffffe;
ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
}
return (status);
}
void ide_set_reset
(
int flag
)
{
return;
}
void ide_set_reset (int flag) {
return;
}
#endif /* of CONFIG_CMDS_IDE */
board/esd/cpci750/local.h
View file @ efe2a4d5
/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
* Ingo Assmus <ingo.assmus@keymile.com>
*
* See file CREDITS for list of people who contributed to this
* project.
......@@ -35,7 +35,7 @@
/* This tells PPCBoot that the config options are compiled in */
/* #undef ENV_IS_EMBEDDED */
/* Don't touch this! PPCBOOT figures this out based on other
/* Don't touch this! PPCBOOT figures this out based on other
* magic. */
/* Uncomment and define any of the below options */
......
board/esd/cpci750/misc.S
View file @ efe2a4d5
......@@ -158,13 +158,13 @@ board_asm_init:
rlwinm r3, r3, 16, 16, 31
lis r4, CFG_GT_REGS@h
ori r4, r4, CFG_GT_REGS@l
li r5, INTEGRATED_SRAM_BASE_ADDR
stwbrx r3, r5, r4
li r5, INTEGRATED_SRAM_BASE_ADDR
stwbrx r3, r5, r4
2: lwbrx r6, r5, r4
cmp cr0, r3, r6
bne 2b
bne 2b
/* done! */
blr
#endif
......
board/esd/cpci750/sdram_init.c
View file @ efe2a4d5
This diff is collapsed.
board/esd/cpci750/serial.c
View file @ efe2a4d5
......@@ -4,7 +4,7 @@
*
* modified for marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*
*
* modified for cpci750 board by
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
......
board/esd/hh405/hh405.c
View file @ efe2a4d5
......@@ -278,13 +278,13 @@ int misc_init_r (void)
udelay(1000);
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
/*
* Enable power on PS/2 interface (with reset)
*/
*fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++)
udelay(1000);
*fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
/*
* Enable power on PS/2 interface (with reset)
*/
*fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++)
udelay(1000);
*fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
/*
* Get contrast value from environment variable
......
board/esd/hub405/hub405.c
View file @ efe2a4d5
......@@ -86,7 +86,7 @@ int misc_init_r (void)
*duart2_mcr = 0x08;
*duart3_mcr = 0x08;
/*
/*
* Set RS232/RS422 control (RS232 = high on GPIO)
*/
val = in32(GPIO0_OR);
......
board/esd/pci405/pci405.c
View file @ efe2a4d5
......@@ -293,7 +293,7 @@ int misc_init_r (void)
*/
#define PCI0_BRDGOPT1 0x4a
pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
// pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60);
/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
#define plb0_acr 0x87
/*
......@@ -303,10 +303,10 @@ int misc_init_r (void)
#if 0 /* test-only */
printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
// mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000);
/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
#endif
// printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
/* printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */ */
#endif
free(dst);
......
board/esd/pci405/writeibm.S
View file @ efe2a4d5
......@@ -50,186 +50,174 @@
write_without_sync:
/*
* Write one values to host via pci busmastering
* ptr = 0xc0000000 -> 0x01000000 (PCI)
* *ptr = 0x01234567;
* ptr = 0xc0000000 -> 0x01000000 (PCI)
* *ptr = 0x01234567;
*/
addi r31,0,0
lis r31,0xc000
addi r31,0,0
lis r31,0xc000
start1:
lis r0,0x0123
ori r0,r0,0x4567
stw r0,0(r31)