Commit f11033e7 authored by Wolfgang Denk's avatar Wolfgang Denk Committed by Wolfgang Denk
Browse files

Merge with /home/hs/SC3/u-boot

Some code cleanup.
parents ddd41233 ca43ba18
commit 5a5c56986a9ccf71642c8b6374eb18487b15fecd
Author: Stefan Roese <sr@denx.de>
Date: Mon Jan 15 09:46:29 2007 +0100
[PATCH] Fix 440SPe rev B detection from previous patch
Signed-off-by: Stefan Roese <sr@denx.de>
commit a443d31410c571ee8f970da819a44d698fdd6b1f
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sun Jan 14 13:35:31 2007 +0100
[FIX] correct I2C Writes for the LM81 Sensor.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 0bba5452835f19a61204edcda3a58112fd8e2208
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sat Jan 13 11:17:10 2007 +0100
Undo commit 3033ebb2: reset command does not take any arguments
Haiying Wang's modification to the reset command was broken, undo it.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 95981778cff0038fd9941044d6a3eda810e33258
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 08:01:03 2007 +0100
[PATCH] Update 440SP(e) cpu revisions
Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 77ddc5b9afb325262fd88752ba430a1dded1f0c7
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:59:56 2007 +0100
[PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 36adff362c2c0141ff8a810d42a7e478f779130f
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:59:19 2007 +0100
[PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
commit e0b9ea8c8a294de6a5350ae638879d24b5b709d6
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:57:51 2007 +0100
[PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 6abaee42621c07e81a2cd189ad4368b5e8c50280
Author: Reinhard Thies <Reinhard.Thies@web.de>
Date: Wed Jan 10 14:41:14 2007 +0100
Adjusted default environment for cam5200 board.
commit bab5a90d4ccc1a46a8127b867fa59028cc623ad9
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Jan 10 15:35:52 2007 +0100
Update CHANGELOG
commit 787fa15860a57833e50bd30555079a9cd4e519b8
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Jan 10 01:28:39 2007 +0100
......@@ -12,6 +99,14 @@ Date: Wed Jan 10 01:28:39 2007 +0100
Also correct the decoding of the keypad status. With this update, the
key that will trigger the update is Column 2, Row 2.
commit d9384de2f571046e71081bae22b49e3d5ca2e3d5
Author: Marian Balakowicz <m8@semihalf.com>
Date: Wed Jan 10 00:26:15 2007 +0100
CAM5200 flash driver modifications:
- use CFI driver (replaces custom flash driver) for main 'cam5200' target
- add second build target 'cam5200_niosflash' which still uses custom driver
commit 67fea022fa957f59653b5238c7496f80a6b70432
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 16:02:48 2007 +0100
......@@ -206,6 +301,14 @@ Date: Thu Dec 21 17:17:02 2006 +0100
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 6dedf3d49dd14c3bf541c8ecee7ffaac5f0e1d6c
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Thu Dec 21 16:14:48 2006 +0100
[PATCH] Add support for the UC101 board from MAN.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit c84bad0ef60e7055ab0bd49b93069509cecc382a
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Dec 20 00:29:43 2006 +0100
......
......@@ -1200,6 +1200,9 @@ sequoia_nand_config: unconfig
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
solidcard3_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx solidcard3
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
......
......@@ -86,7 +86,6 @@
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
......@@ -355,8 +354,6 @@
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
......
......@@ -92,8 +92,8 @@ static void sdram_start (int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
......@@ -291,7 +291,7 @@ int misc_init_r (void)
}
#ifdef CONFIG_AUTO_UPDATE
do_auto_update();
do_auto_update();
#endif
return (0);
}
......
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o sc3nand.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000
/*------------------------------------------------------------------------------+
*
* This souce code has been made available to you by EuroDesign
* (www.eurodsn.de). It's based on the original IBM source code, so
* this follows:
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*------------------------------------------------------------------------------- */
#include <config.h>
#include <ppc4xx.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/**
* ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
*
* IMPORTANT: For pass1 this code must run from cache since you can not
* reliably change a peripheral banks timing register (pbxap) while running
* code from that bank. For ex., since we are running from ROM on bank 0, we
* can NOT execute the code that modifies bank 0 timings from ROM, so
* we run it from cache.
*
* Bank 0 - Boot-Flash
* Bank 1 - NAND-Flash
* Bank 2 - ISA bus
* Bank 3 - Second Flash
* Bank 4 - USB controller
*/
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
* We need the current boot up configuration to set correct
* timings into internal flash and external flash
*/
mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
0 0 -> 8 bit external ROM
0 1 -> 16 bit internal ROM */
addi r4,0,2
srw r24,r24,r4 /* shift right r24 two positions */
andi. r24,r24,0x06000
/*
* All calculations are based on 33MHz EBC clock.
*
* First, create a "very slow" timing (~250ns) with burst mode enabled
* This is need for the external flash access
*/
lis r25,0x0800
ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
/*
* Second, create a fast timing:
* 90ns first cycle - 3 clock access
* and 90ns burst cycle, plus 1 clock after the last access
* This is used for the internal access
*/
lis r26,0x8900
ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
/*
* We can't change settings on CS# if we currently use them.
* -> load a few instructions into cache and run this code from cache
*/
mflr r4 /* save link register */
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
mtlr r4 /* restore link register */
addi r4,0,14 /* set ctr to 10; used to prefetch */
mtctr r4 /* 10 cache lines to fit this function
in cache (gives us 8x10=80 instructions) */
..ebcloop:
icbt r0,r3 /* prefetch cache line for addr in r3 */
addi r3,r3,32 /* move to next cache line */
bdnz ..ebcloop /* continue for 10 cache lines */
/*
* Delay to ensure all accesses to ROM are complete before changing
* bank 0 timings. 200usec should be enough.
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
*/
lis r3,0x0
ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
mtctr r3
..spinlp:
bdnz ..spinlp /* spin loop */
/*-----------------------------------------------------------------------
* Memory Bank 0 (BOOT-ROM) initialization
* 0xFFEF00000....0xFFFFFFF
* We only have to change the timing. Mapping is ok by boot-strapping
*----------------------------------------------------------------------- */
li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */
mtdcr ebccfga,r4
mr r4,r26 /* assume internal fast flash is boot flash */
cmpwi r24,0x2000 /* assumption true? ... */
beq 1f /* ...yes! */
mr r4,r25 /* ...no, use the slow variant */
mr r25,r26 /* use this for the other flash */
1:
mtdcr ebccfgd,r4 /* change timing now */
li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */
mtdcr ebccfga,r4
mfdcr r4,ebccfgd
lis r3,0x0001
ori r3,r3,0x8000 /* allow reads and writes */
or r4,r4,r3
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 3 (Second-Flash) initialization
* 0xF0000000...0xF01FFFFF -> 2MB
*----------------------------------------------------------------------- */
li r4,pb3ap /* Peripheral Bank 1 Access Parameter */
mtdcr ebccfga,r4
mtdcr ebccfgd,r2 /* change timing */
li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */
mtdcr ebccfga,r4
lis r4,0xF003
ori r4,r4,0x8000
/*
* Consider boot configuration
*/
xori r24,r24,0x2000 /* invert current bus width */
or r4,r4,r24
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 1 (NAND-Flash) initialization
* 0x77D00000...0x77DFFFFF -> 1MB
* - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
* - the setup time is 0ns
* - the hold time is 15ns
* ->
* - TWT = 0
* - CSN = 0
* - OEN = 0
* - WBN = 0
* - WBF = 0
* - TH = 1
* ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
*----------------------------------------------------------------------- */
li r4,pb1ap /* Peripheral Bank 1 Access Parameter */
mtdcr ebccfga,r4
lis r4,0x0000
ori r4,r4,0x0200
mtdcr ebccfgd,r4
li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */
mtdcr ebccfga,r4
lis r4,0x77D1
ori r4,r4,0x8000
mtdcr ebccfgd,r4
/* USB init (without acceleration) */
#ifndef CONFIG_ISP1161_PRESENT
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x0180
ori r4,r4,0x5940
mtdcr ebccfgd,r4
#endif
/*-----------------------------------------------------------------------
* Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
* 0x78000000...0x7BFFFFFF -> 64 MB
* Wir arbeiten bei 33 MHz -> 30ns
*-----------------------------------------------------------------------
A7 (ppc notation) or A24 (standard notation) decides about
the type of access:
A7/A24=0 -> memory cycle
A7/ /A24=1 -> I/O cycle
*/
li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */
mtdcr ebccfga,r4
/*
We emulate an ISA access
1. Address active
2. wait 0 EBC clocks -> CSN=0
3. set CS#
4. wait 0 EBC clock -> OEN/WBN=0
5. set OE#/WE#
6. wait 4 clocks (ca. 90ns) and for Ready signal
7. hold for 4 clocks -> TH=4
*/
#if 1
/* faster access to isa-bus */
lis r4,0x0180
ori r4,r4,0x5940
#else
lis r4,0x0100
ori r4,r4,0x0340
#endif
mtdcr ebccfgd,r4
#ifdef IDE_USES_ISA_EMULATION
li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
#endif
li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x780B
ori r4,r4,0xA000
mtdcr ebccfgd,r4
/*
* the other areas are only 1MiB in size
*/
lis r4,0x7401
ori r4,r4,0xA000
li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7401
ori r4,r4,0xA000
mtdcr ebccfgd,r4
li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7411
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#ifndef CONFIG_ISP1161_PRESENT
li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7421
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
#ifdef IDE_USES_ISA_EMULATION
li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
#endif
/*-----------------------------------------------------------------------
* Memory bank 4: USB controller Philips ISP6111
* 0x77C00000 ... 0x77CFFFFF
*
* The chip is connected to:
* - CPU CS#4
* - CPU IRQ#2
* - CPU DMA 3
*
* Timing:
* - command to first data: 300ns. Software must ensure this timing!
* - Write pulse: 26ns
* - Read pulse: 33ns
* - read cycle time: 150ns
* - write cycle time: 140ns
*
* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
*
* |- 300ns --|
* |---- 420ns ---|---- 420ns ---| cycle
* CS ############:###____#######:###____#######
* OE ############:####___#######:####___#######
* WE ############:####__########:####__########
*
* ----> 2 clocks RD/WR pulses: 60ns
* ----> CSN: 3 clock, 90ns
* ----> OEN: 1 clocks (read cycle)
* ----> WBN: 1 clocks (write cycle)
* ----> WBE: 2 clocks
* ----> TH: 7 clock, 210ns
* ----> TWT: 7 clocks
*----------------------------------------------------------------------- */
#ifdef CONFIG_ISP1161_PRESENT
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x030D
ori r4,r4,0x5E80
mtdcr ebccfgd,r4
li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */
mtdcr ebccfga,r4
lis r4,0x77C1
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
#ifndef IDE_USES_ISA_EMULATION
/*-----------------------------------------------------------------------
* Memory Bank 5 used for IDE access
*
* Timings for IDE Interface
*
* SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
* 70 165 30 PIO-Mode 0, [ns]
* 3 6 1 [Cycles] ----> AP=0x040C0200
* 50 125 20 PIO-Mode 1, [ns]
* 2 5 1 [Cycles] ----> AP=0x03080200
* 30 100 15 PIO-Mode 2, [ns]
* 1 4 1 [Cycles] ----> AP=0x02040200
* 30 80 10 PIO-Mode 3, [ns]
* 1 3 1 [Cycles] ----> AP=0x01840200
* 25 70 10 PIO-Mode 4, [ns]
* 1 3 1 [Cycles] ----> AP=0x01840200
*
*----------------------------------------------------------------------- */
li r4,pb5ap
mtdcr ebccfga,r4
lis r4,0x040C
ori r4,r4,0x0200
mtdcr ebccfgd,r4
li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */
mtdcr ebccfga,r4
lis r4,0x7A01
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
/*
* External Peripheral Control Register
*/
li r4,epcr
mtdcr ebccfga,r4
lis r4,0xB84E
ori r4,r4,0xF000
mtdcr ebccfgd,r4
/*
* drive POST code
*/
lis r4,0x7900
ori r4,r4,0x0080