Commit f2ffe7da authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of http://git.denx.de/u-boot-sunxi

parents 1fc4e6f4 b366fb92
......@@ -180,6 +180,21 @@ void clock_set_pll1(unsigned int hz)
}
#endif
void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (clk == 0) {
clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
return;
}
/* PLL3 rate = 3000000 * m */
writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
}
unsigned int clock_get_pll5p(void)
{
struct sunxi_ccm_reg *const ccm =
......@@ -200,3 +215,15 @@ unsigned int clock_get_pll6(void)
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
{
int pll = clock_get_pll5p();
int div = 1;
while ((pll / div) > hz)
div++;
writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
CCM_DE_CTRL_M(div), clk_cfg);
}
......@@ -127,6 +127,23 @@ void clock_set_pll1(unsigned int clk)
}
#endif
void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
if (clk == 0) {
clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
return;
}
/* PLL3 rate = 24000000 * n / m */
writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
&ccm->pll3_cfg);
}
void clock_set_pll5(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
......@@ -151,3 +168,15 @@ unsigned int clock_get_pll6(void)
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
{
int pll = clock_get_pll6() * 2;
int div = 1;
while ((pll / div) > hz)
div++;
writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
clk_cfg);
}
......@@ -428,9 +428,9 @@ static void dramc_clock_output_en(u32 on)
#ifdef CONFIG_MACH_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
else
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
#endif
}
......
......@@ -142,9 +142,6 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
&mctl_phy->ptr0);
/* Unknown magic performed by boot0 */
if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2)
setbits_le32(&mctl_phy->ptr0, 1 << 18);
writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
......
......@@ -25,9 +25,11 @@
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_uart(void);
#endif
......
......@@ -62,7 +62,7 @@ struct sunxi_ccm_reg {
u32 gps_clk_cfg; /* 0xd0 */
u32 spi3_clk_cfg; /* 0xd4 */
u8 res5[0x28];
u32 dram_clk_cfg; /* 0x100 */
u32 dram_clk_gate; /* 0x100 */
u32 be0_clk_cfg; /* 0x104 */
u32 be1_clk_cfg; /* 0x108 */
u32 fe0_clk_cfg; /* 0x10c */
......@@ -186,12 +186,20 @@ struct sunxi_ccm_reg {
/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
#define AHB_GATE_OFFSET_LCD0 4
#define CCM_AHB_GATE_GPS (0x1 << 26)
#define CCM_AHB_GATE_SDRAM (0x1 << 14)
#define CCM_AHB_GATE_DLL (0x1 << 15)
#define CCM_AHB_GATE_ACE (0x1 << 16)
#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0)
#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15)
#define CCM_PLL3_CTRL_EN (0x1 << 31)
#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
......@@ -253,6 +261,34 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
#define CCM_LCD_CH0_CTRL_RST (0x1 << 30)
#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
/* We leave bit 11 set to 0, so sclk1 == sclk2 */
#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
/* Enable / disable both ch1 sclk1 and sclk2 at the same time */
#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15)
#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
#define CCM_HDMI_CTRL_PLL3 (0 << 24)
#define CCM_HDMI_CTRL_PLL7 (1 << 24)
#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
/* No separate ddc gate on sun4i, sun5i and sun7i */
#define CCM_HDMI_CTRL_DDC_GATE 0
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
......@@ -266,4 +302,13 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY1_CLK 0
#define CCM_USB_CTRL_PHY2_CLK 0
/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_DE_CTRL_PLL_MASK (3 << 24)
#define CCM_DE_CTRL_PLL3 (0 << 24)
#define CCM_DE_CTRL_PLL7 (1 << 24)
#define CCM_DE_CTRL_PLL5P (2 << 24)
#define CCM_DE_CTRL_RST (1 << 30)
#define CCM_DE_CTRL_GATE (1 << 31)
#endif /* _SUNXI_CLOCK_SUN4I_H */
......@@ -176,13 +176,18 @@ struct sunxi_ccm_reg {
#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
#define CCM_PLL3_CTRL_EN (0x1 << 31)
#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL5_CTRL_UPD (0x1 << 20)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
#define PLL6_CFG_DEFAULT 0x90041811
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
......@@ -193,17 +198,26 @@ struct sunxi_ccm_reg {
#define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */
#define AHB_GATE_OFFSET_USB_OHCI1 30
#define AHB_GATE_OFFSET_USB_OHCI0 29
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
/* ahb_gate1 offsets */
#define AHB_GATE_OFFSET_DRC0 25
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
#define AHB_GATE_OFFSET_LCD0 4
#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
......@@ -216,6 +230,12 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
......@@ -223,8 +243,35 @@ struct sunxi_ccm_reg {
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
#define CCM_HDMI_CTRL_PLL3 (0 << 24)
#define CCM_HDMI_CTRL_PLL7 (1 << 24)
#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
#define AHB_RESET_OFFSET_MMC2 10
......@@ -232,10 +279,28 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_MMC0 8
#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_DRC0 25
#define AHB_RESET_OFFSET_DE_BE0 12
#define AHB_RESET_OFFSET_HDMI 11
#define AHB_RESET_OFFSET_LCD1 5
#define AHB_RESET_OFFSET_LCD0 4
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
#define APB2_RESET_TWI_SHIFT (0)
#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_DE_CTRL_PLL_MASK (0xf << 24)
#define CCM_DE_CTRL_PLL3 (0 << 24)
#define CCM_DE_CTRL_PLL7 (1 << 24)
#define CCM_DE_CTRL_PLL6_2X (2 << 24)
#define CCM_DE_CTRL_PLL8 (3 << 24)
#define CCM_DE_CTRL_PLL9 (4 << 24)
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
#endif /* _SUNXI_CLOCK_SUN6I_H */
......@@ -99,9 +99,13 @@
#define SUNXI_SCR_BASE 0x01c2c400
#ifndef CONFIG_MACH_SUN6I
#define SUNXI_GPS_BASE 0x01c30000
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
#else
#define SUNXI_GMAC_BASE 0x01c30000
#endif
#define SUNXI_DRAM_COM_BASE 0x01c62000
#define SUNXI_DRAM_CTL0_BASE 0x01c63000
......
/*
* Sunxi platform display controller register and constant defines
*
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_DISPLAY_H
#define _SUNXI_DISPLAY_H
struct sunxi_de_be_reg {
u8 res0[0x800]; /* 0x000 */
u32 mode; /* 0x800 */
u32 backcolor; /* 0x804 */
u32 disp_size; /* 0x808 */
u8 res1[0x4]; /* 0x80c */
u32 layer0_size; /* 0x810 */
u32 layer1_size; /* 0x814 */
u32 layer2_size; /* 0x818 */
u32 layer3_size; /* 0x81c */
u32 layer0_pos; /* 0x820 */
u32 layer1_pos; /* 0x824 */
u32 layer2_pos; /* 0x828 */
u32 layer3_pos; /* 0x82c */
u8 res2[0x10]; /* 0x830 */
u32 layer0_stride; /* 0x840 */
u32 layer1_stride; /* 0x844 */
u32 layer2_stride; /* 0x848 */
u32 layer3_stride; /* 0x84c */
u32 layer0_addr_low32b; /* 0x850 */
u32 layer1_addr_low32b; /* 0x854 */
u32 layer2_addr_low32b; /* 0x858 */
u32 layer3_addr_low32b; /* 0x85c */
u32 layer0_addr_high4b; /* 0x860 */
u32 layer1_addr_high4b; /* 0x864 */
u32 layer2_addr_high4b; /* 0x868 */
u32 layer3_addr_high4b; /* 0x86c */
u32 reg_ctrl; /* 0x870 */
u8 res3[0xc]; /* 0x874 */
u32 color_key_max; /* 0x880 */
u32 color_key_min; /* 0x884 */
u32 color_key_config; /* 0x888 */
u8 res4[0x4]; /* 0x88c */
u32 layer0_attr0_ctrl; /* 0x890 */
u32 layer1_attr0_ctrl; /* 0x894 */
u32 layer2_attr0_ctrl; /* 0x898 */
u32 layer3_attr0_ctrl; /* 0x89c */
u32 layer0_attr1_ctrl; /* 0x8a0 */
u32 layer1_attr1_ctrl; /* 0x8a4 */
u32 layer2_attr1_ctrl; /* 0x8a8 */
u32 layer3_attr1_ctrl; /* 0x8ac */
};
struct sunxi_lcdc_reg {
u32 ctrl; /* 0x00 */
u32 int0; /* 0x04 */
u32 int1; /* 0x08 */
u8 res0[0x04]; /* 0x0c */
u32 frame_ctrl; /* 0x10 */
u8 res1[0x2c]; /* 0x14 */
u32 tcon0_ctrl; /* 0x40 */
u32 tcon0_dclk; /* 0x44 */
u32 tcon0_basic_timing0; /* 0x48 */
u32 tcon0_basic_timing1; /* 0x4c */
u32 tcon0_basic_timing2; /* 0x50 */
u32 tcon0_basic_timing3; /* 0x54 */
u32 tcon0_hv_intf; /* 0x58 */
u8 res2[0x04]; /* 0x5c */
u32 tcon0_cpu_intf; /* 0x60 */
u32 tcon0_cpu_wr_dat; /* 0x64 */
u32 tcon0_cpu_rd_dat0; /* 0x68 */
u32 tcon0_cpu_rd_dat1; /* 0x6c */
u32 tcon0_ttl_timing0; /* 0x70 */
u32 tcon0_ttl_timing1; /* 0x74 */
u32 tcon0_ttl_timing2; /* 0x78 */
u32 tcon0_ttl_timing3; /* 0x7c */
u32 tcon0_ttl_timing4; /* 0x80 */
u32 tcon0_lvds_intf; /* 0x84 */
u32 tcon0_io_polarity; /* 0x88 */
u32 tcon0_io_tristate; /* 0x8c */
u32 tcon1_ctrl; /* 0x90 */
u32 tcon1_timing_source; /* 0x94 */
u32 tcon1_timing_scale; /* 0x98 */
u32 tcon1_timing_out; /* 0x9c */
u32 tcon1_timing_h; /* 0xa0 */
u32 tcon1_timing_v; /* 0xa4 */
u32 tcon1_timing_sync; /* 0xa8 */
u8 res3[0x44]; /* 0xac */
u32 tcon1_io_polarity; /* 0xf0 */
u32 tcon1_io_tristate; /* 0xf4 */
};
struct sunxi_hdmi_reg {
u32 version_id; /* 0x000 */
u32 ctrl; /* 0x004 */
u32 irq; /* 0x008 */
u32 hpd; /* 0x00c */
u32 video_ctrl; /* 0x010 */
u32 video_size; /* 0x014 */
u32 video_bp; /* 0x018 */
u32 video_fp; /* 0x01c */
u32 video_spw; /* 0x020 */
u32 video_polarity; /* 0x024 */
u8 res0[0x1d8]; /* 0x028 */
u32 pad_ctrl0; /* 0x200 */
u32 pad_ctrl1; /* 0x204 */
u32 pll_ctrl; /* 0x208 */
u32 pll_dbg0; /* 0x20c */
};
/*
* DE-BE register constants.
*/
#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
#define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
#define SUNXI_DE_BE_MODE_START (1 << 1)
#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
/*
* LCDC register constants.
*/
#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
/*
* HDMI register constants.
*/
#define SUNXI_HDMI_X(x) (((x) - 1) << 0)
#define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
#define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
#define SUNXI_HDMI_HPD_DETECT (1 << 0)
#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
#ifdef CONFIG_MACH_SUN6I
#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
#else
#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
#endif
#ifdef CONFIG_MACH_SUN4I
#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
#elif defined CONFIG_MACH_SUN6I
#define SUNXI_HDMI_PAD_CTRL1 0x01ded030
#else
#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
#endif
#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
#ifdef CONFIG_MACH_SUN6I
#define SUNXI_HDMI_PLL_CTRL 0xba48a308
#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
#else
#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
#endif
#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
int sunxi_simplefb_setup(void *blob);
#endif /* _SUNXI_DISPLAY_H */
......@@ -134,6 +134,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_OUTPUT 1
#define SUNXI_GPA0_EMAC 2
#define SUN6I_GPA0_GMAC 2
#define SUN7I_GPA0_GMAC 5
#define SUNXI_GPB0_TWI0 2
......
......@@ -24,6 +24,7 @@ config MACH_SUN7I
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I
bool "sun8i (Allwinner A23)"
......@@ -215,4 +216,18 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
config VIDEO
boolean "Enable graphical uboot console on HDMI"
default y
---help---
Say Y here to add support for using a cfb console on the HDMI output
found on most sunxi devices.
config USB_KEYBOARD
boolean "Enable USB keyboard support"
default y
---help---
Say Y here to add support for using a USB keyboard (typically used
in combination with a graphical console on HDMI).
endif
......@@ -76,6 +76,8 @@ void scsi_init(void)
#ifdef CONFIG_SATAPWR
gpio_request(CONFIG_SATAPWR, "satapwr");
gpio_direction_output(CONFIG_SATAPWR, 1);
/* Give attached sata device time to power-up to avoid link timeouts */
mdelay(500);
#endif
if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
......
......@@ -24,6 +24,7 @@
#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
......@@ -237,3 +238,12 @@ int misc_init_r(void)
return 0;
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
return sunxi_simplefb_setup(blob);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */
......@@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
#ifndef CONFIG_MACH_SUN6I
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
#else
setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
#endif
/* Set MII clock */
#ifdef CONFIG_RGMII
......@@ -33,6 +38,7 @@ int sunxi_gmac_initialize(bd_t *bis)
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
#endif
#ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
......@@ -43,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis)
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_RGMII
/* Configure sun6i RGMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
sunxi_gpio_set_drv