Commit f4863a7a authored by wdenk's avatar wdenk
Browse files

* Patch by liang a lei, 9 Jan 2004:

  Fix Intel 28F128J3 ID in include/flash.h

* Patch by Masami Komiya, 09 Jan 2004:
  add support for TB0229 board (NEC VR4131 MIPS processor)

* Patch by Leon Kukovec, 12 Dec 2003:
  changed extern __inline__ into static __inline__ in
  include/linux/byteorder/swab.h
parent ba56f625
......@@ -2,6 +2,16 @@
Changes since U-Boot 1.0.1:
======================================================================
* Patch by liang a lei, 9 Jan 2004:
Fix Intel 28F128J3 ID in include/flash.h
* Patch by Masami Komiya, 09 Jan 2004:
add support for TB0229 board (NEC VR4131 MIPS processor)
* Patch by Leon Kukovec, 12 Dec 2003:
changed extern __inline__ into static __inline__ in
include/linux/byteorder/swab.h
* Patch by Travis Sawyer, 30 Dec 2003:
Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
select MDI port based on enabled EMAC device.
......
......@@ -1027,6 +1027,9 @@ incaip_config: unconfig
}
@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
tb0229_config: unconfig
@./mkconfig $(@:_config=) mips mips tb0229
#########################################################################
## MIPS64 5Kc
#########################################################################
......
#
# (C) Masami Komiya <mkomiya@sonare.it> 2004
#
# (C) Copyright 2003-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o vr4131-pci.o
SOBJS = memsetup.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
#
# (C) Masami Komiya <mkomiya@sonare.it> 2004
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# ROM version
TEXT_BASE = 0xBFC00000
# RAM version
#TEXT_BASE = 0x80400000
This diff is collapsed.
/*
* Memory sub-system initialization code for TANBAC Evaluation board TB0229.
*
* Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
.globl memsetup
memsetup:
/* BCUCNTREG1 = 0x0040 */
la t0, 0xaf000000
li t1, 0x0040
sh t1, 0(t0)
/* ROMSIZEREG = 0x3333 */
la t0, 0xaf000004
li t1, 0x3333
sh t1, 0(t0)
/* ROMSPEEDREG = 0x3003 */
la t0, 0xaf000006
li t1, 0x3003
sh t1, 0(t0)
/* BCUCNTREG3 = 0 */
la t0, 0xaf000016
li t1, 0x0000
sh t1, 0(t0)
/* CMUCLKMSK */
la t0, 0xaf000060
li t1, 0x39a2
sh t1, 0(t0)
/* PMUCNTREG */
la t0, 0xaf0000c2
li t1, 0x0006
sh t1, 0(t0)
/* SDRAMMODEREG = 0x8029 */
la t0, 0xaf000400
li t1, 0x8029
sh t1, 0(t0)
/* SDRAMCNTREG = 0x2322 */
la t0, 0xaf000402
li t1, 0x2322
sh t1, 0(t0)
/* BCURFCNTREG = 0x0106 */
la t0, 0xaf000404
li t1, 0x0106
sh t1, 0(t0)
/* RAMSZEREG = 0x5555 (64MB Bank) */
la t0, 0xaf000408
li t1, 0x5555
sh t1, 0(t0)
j ra
nop
/*
* Board initialize code for TANBAC Evaluation board TB0229.
*
* (C) Masami Komiya <mkomiya@sonare.it> 2004
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include <common.h>
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <pci.h>
unsigned long mips_io_port_base = 0;
#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board (void)
{
init_vr4131_pci(&hose);
}
#endif
long int initdram(int board_type)
{
return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
}
int checkboard (void)
{
printf("Board: TANBAC TB0229 ");
printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
return 0;
}
/*
* (C) Masami Komiya <mkomiya@sonare.it> 2004
*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}
/*
* VR4131 PCIU support code for TANBAC Evaluation board TB0229.
*
* (C) Masami Komiya <mkomiya@sonare.it> 2004
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include <common.h>
#include <pci.h>
#include <asm/addrspace.h>
#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00)
#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04)
#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08)
#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c)
#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10)
#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14)
#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18)
#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c)
#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24)
#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28)
#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c)
#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30)
#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34)
#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38)
#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c)
#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60)
#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10)
#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14)
#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18)
/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */
/*#define VR4122_PCI_HOST_BASE 0xa0000000 */
volatile unsigned int *pciconfigaddr;
volatile unsigned int *pciconfigdata;
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
/*
* Access PCI Configuration Register for VR4131
*/
static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
u32 * data)
{
u32 bus;
u32 device;
bus = ((dev & 0xff0000) >> 16);
device = ((dev & 0xf800) >> 11);
if (bus == 0) {
/* Type 0 Configuration */
*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
} else {
/* Type 1 Configuration */
*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
}
if (access_type == PCI_ACCESS_WRITE) {
*VR4131_PCICONFDREG = *data;
} else {
*data = *VR4131_PCICONFDREG;
}
return (0);
}
static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
{
u32 data;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = (data >> ((reg & 3) << 3)) & 0xff;
return 0;
}
static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
{
u32 data;
if (reg & 1)
return -1;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = (data >> ((reg & 3) << 3)) & 0xffff;
return 0;
}
static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
u32 * val)
{
u32 data = 0;
if (reg & 3)
return -1;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = data;
return (0);
}
static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
{
u32 data = 0;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
((reg & 3) << 3));
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return 0;
}
static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
{
u32 data = 0;
if (reg & 1)
return -1;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
((reg & 3) << 3));
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return 0;
}
static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
{
u32 data;
if (reg & 3) {
return -1;
}
data = val;
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return (0);
}
/*
* Initialize VR4131 PCIU
*/
vr4131_pciu_init ()
{
/* PCI clock */
*VR4131_PCICLKSELREG = 0x00000002;
/* PCI memory and I/O space */
*VR4131_PCIMMAW1REG = 0x100F9010;
*VR4131_PCIMMAW2REG = 0x140FD014;
*VR4131_PCIMIOAWREG = 0x160FD000;
/* Target memory window */
*VR4131_PCITAW1REG = 0x00081000; /* 64MB */
*VR4131_PCITAW2REG = 0x00000000;
*VR4131_MAILBAREG = 0UL;
*VR4131_PCIMBA1REG = 0UL;
*VR4131_PCITRDYREG = 0x00008004;
*VR4131_PCIENREG = 0x00000004; /* PCI enable */
*VR4131_COMMANDREG = 0x02000007;
}
/*
* Initialize Module
*/
void init_vr4131_pci (struct pci_controller *hose)
{
hose->first_busno = 0;
hose->last_busno = 0xff;
vr4131_pciu_init (); /* Initialize VR4131 PCIU */
/* PCI memory space #1 */
pci_set_region (hose->regions + 0,
0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
/* PCI memory space #2 */
pci_set_region (hose->regions + 1,
0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (hose->regions + 2,
0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
/* System memory space */
pci_set_region (hose->regions + 3,
0x00000000,
0x80000000,
0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 4;
hose->read_byte = vr4131_pci_read_config_byte;
hose->read_word = vr4131_pci_read_config_word;
hose->read_dword = vr4131_pci_read_config_dword;
hose->write_byte = vr4131_pci_write_config_byte;
hose->write_word = vr4131_pci_write_config_word;
hose->write_dword = vr4131_pci_write_config_dword;
pci_register_hose (hose);
hose->last_busno = pci_hose_scan (hose);
return;
}
......@@ -30,7 +30,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_INCA_IP)
*INCA_IP_WDT_RST_REQ = 0x3f;
#elif defined(CONFIG_PURPLE)
#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
void (*f)(void) = (void *) 0xbfc00000;
f();
......
......@@ -214,7 +214,11 @@ reset:
mtc0 zero, CP0_WATCHHI
/* STATUS register */
#ifdef CONFIG_TB0229
li k0, ST0_CU0
#else
mfc0 k0, CP0_STATUS
#endif
li k1, ~ST0_IE
and k0, k1
mtc0 k0, CP0_STATUS
......
......@@ -44,7 +44,7 @@
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
#ifdef CONFIG_AU1X00
#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
......
/*
* (C) Copyright 2003
* Masami Komiya <mkomiya@sonare.it>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Config header file for TANBAC TB0229 board using an VR4131 CPU module
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_TB0229 1 /* on a TB0229 Board */
#ifndef CPU_CLOCK_RATE
#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */
#endif
#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */
#define CONFIG_CONS_INDEX 1
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \
"echo Type \"run netboot_initrd\" for the network boot with initrd;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo Type \"run flash_local\" to mount local root filesystem;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netboot=dhcp;tftp;run netargs; bootm\0" \