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Commit f61f1e15 authored by Stefan Roese's avatar Stefan Roese
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

parents ec081c2c f82642e3
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CHANGELOG
View file @ f61f1e15
commit f7a35a60cf45491871a5c28e9ad24db005487857
Author: Heiko Schocher <hs@denx.de>
Date: Fri Oct 17 18:24:06 2008 +0200
mgcoge: add redundant environment sector
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c2537ee85954af9d036b18b644f3e18d837bf4a5
Author: Heiko Schocher <hs@denx.de>
Date: Fri Oct 17 18:23:27 2008 +0200
mgsuvd: update size of environment
Signed-off-by: Heiko Schocher <hs@denx.de>
commit fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d
Author: Lepcha Suchit <Suchit.Lepcha@freescale.com>
Date: Thu Oct 16 13:38:00 2008 -0500
83xx NAND boot: wait for LTESR[CC]
At least some revisions of the 8313, and possibly other chips, do not
wait for all pages of the initial 4K NAND region to be loaded before
beginning execution; thus, we wait for it before branching out of the
first NAND page.
This fixes warm reset problems when booting from NAND on 8313erdb.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
commit bf29e0ea0af03d593c64614136acc723a7a022a2
Author: Yuri Tikhonov <yur@emcraft.com>
Date: Fri Oct 17 12:54:18 2008 +0200
ppc4xx: PPC44x MQ initialization
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.
Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit f7d190b1c0b3ab7fc53074ad2862f7de99de37ff
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Oct 16 21:58:50 2008 -0500
85xx: Using proper I2C source clock divider for MPC8544
The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
bit 26, instead it should be bit 28. This caused in incorrect
interpretation of the i2c_clk which is the same as the SEC clk on
MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported
in PORDEVSR2.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 42653b826adb319a1df06e24ef26096b2a5d9d2a
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Oct 16 21:58:49 2008 -0500
Revert "85xx: Using proper I2C source clock divider for MPC8544"
This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159.
The fix introduced by this patch is not correct. The problem is
that the documentation is not correct for the MPC8544 with regards
to which bit in PORDEVSR2 is for the SEC_CFG.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 2179c4766bffeece98e5e92040629a96c97e230c
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Wed Oct 15 10:19:41 2008 -0500
85xx: Fix compile warning
mpc8536ds.c: In function 'is_sata_supported':
mpc8536ds.c:614: warning: unused variable 'devdisr'
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 9029b68f3f81b3013044f167ea025e836e6c8c0e
Author: Jason Jin <Jason.jin@freescale.com>
Date: Wed Oct 15 10:40:24 2008 +0800
Fix the function conflict in x86emu when DEBUG is on
The function parse_line() in common/main.c was exposed globally by commit
6636b62a6efc7f14e6e788788631ae7a7fca4537, Result in conflict with the same
name funciton in drivers/bios_emulator/x86emu/debug.c when define the DEBUG.
This patch fix this by renaming the function in the debug.c file.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit b4dbacf69a669a17487054552fc2761149dd6767
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Oct 15 15:50:45 2008 +0200
Coding Style cleanup, update CHANGELOG, prepare 2008.10-rc3
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 374b9038293d01d8744a46af9b7854a6fd99b228
Author: Heiko Schocher <hs@denx.de>
Date: Wed Oct 15 09:51:19 2008 +0200
Makefile
View file @ f61f1e15
......@@ -24,7 +24,7 @@
VERSION = 2008
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
......@@ -243,9 +243,11 @@ endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
LIBS += cpu/mpc8xxx/ddr/libddr.a
TAG_SUBDIRS += cpu/mpc8xxx
endif
ifeq ($(CPU),mpc86xx)
LIBS += cpu/mpc8xxx/ddr/libddr.a
TAG_SUBDIRS += cpu/mpc8xxx
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
......@@ -922,7 +924,7 @@ MBX860T_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
mgsuvd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
MHPC_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
......@@ -1701,12 +1703,12 @@ ISPAN_config \
ISPAN_REVB_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _REVB_,$@)" ] ; then \
echo "#define CFG_REV_B" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
mgcoge_config : unconfig
@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge
@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge keymile
MPC8260ADS_config \
MPC8260ADS_lowboot_config \
......@@ -1728,8 +1730,8 @@ PQ2FADS-ZU_66MHz_lowboot_config \
@mkdir -p $(obj)include
@mkdir -p $(obj)board/freescale/mpc8260ads
$(if $(findstring PQ2FADS,$@), \
@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
@echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
$(if $(findstring MHz,$@), \
@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
$(if $(findstring VR,$@), \
......@@ -1981,19 +1983,19 @@ M54451EVB_stmicro_config : unconfig
M54451EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
if [ "$${FLASH}" = "SPANSION" ] ; then \
echo "#define CFG_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
$(XECHO) "... with SPANSION boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
@$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale
M54455EVB_config \
......@@ -2015,25 +2017,25 @@ M54455EVB_stm33_config : unconfig
M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \
esac; \
if [ "$${FLASH}" = "INTEL" ] ; then \
echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with INTEL boot..." ; \
fi; \
if [ "$${FLASH}" = "ATMEL" ] ; then \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with ATMEL boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
$(XECHO) "... with $${FREQ}Hz input clock"
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
......@@ -2053,20 +2055,20 @@ M5475GFE_config : unconfig
M5475FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
M5475GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
esac; \
echo "#define CFG_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
if [ "$${RAM1}" != "0" ] ; then \
echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
fi; \
if [ "$${CODE}" != "0" ] ; then \
echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
fi; \
if [ "$${VID}" == "1" ] ; then \
echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
fi; \
if [ "$${USB}" == "1" ] ; then \
echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
......@@ -2088,20 +2090,20 @@ M5485HFE_config : unconfig
M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
esac; \
echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
if [ "$${RAM1}" != "0" ] ; then \
echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
fi; \
if [ "$${CODE}" != "0" ] ; then \
echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
fi; \
if [ "$${VID}" == "1" ] ; then \
echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
fi; \
if [ "$${USB}" == "1" ] ; then \
echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
......@@ -2120,11 +2122,11 @@ MPC8313ERDB_NAND_66_config: unconfig
@mkdir -p $(obj)board/freescale/mpc8313erdb
@if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "...33M ..." ; \
echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
$(XECHO) -n "...66M..." ; \
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _NAND_,$@)" ] ; then \
$(XECHO) -n "...NAND..." ; \
......
README
View file @ f61f1e15
This diff is collapsed.
doc/README.nios_CFG_NIOS_CPU → README.nios_CONFIG_SYS_NIOS_CPU
View file @ f61f1e15
......@@ -11,117 +11,117 @@ Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
C O R E N I O S S D K [1],[7]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_CLK nasys_clock_freq
CFG_NIOS_CPU_ICACHE nasys_icache_size
CFG_NIOS_CPU_DCACHE nasys_dcache_size
CFG_NIOS_CPU_REG_NUMS nasys_nios_num_regs
CFG_NIOS_CPU_MUL __nios_use_multiply__
CFG_NIOS_CPU_MSTEP __nios_use_mstep__
CFG_NIOS_CPU_STACK nasys_stack_top
CFG_NIOS_CPU_VEC_BASE nasys_vector_table
CFG_NIOS_CPU_VEC_SIZE nasys_vector_table_size
CFG_NIOS_CPU_VEC_NUMS
CFG_NIOS_CPU_RST_VECT nasys_reset_address
CFG_NIOS_CPU_DBG_CORE nasys_debug_core
CFG_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
CFG_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
CFG_NIOS_CPU_ROM_BASE na_boot_monitor_rom
CFG_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
CFG_NIOS_CPU_OCI_BASE nasys_oci_core
CFG_NIOS_CPU_OCI_SIZE
CFG_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
CONFIG_SYS_NIOS_CPU_CLK nasys_clock_freq
CONFIG_SYS_NIOS_CPU_ICACHE nasys_icache_size
CONFIG_SYS_NIOS_CPU_DCACHE nasys_dcache_size
CONFIG_SYS_NIOS_CPU_REG_NUMS nasys_nios_num_regs
CONFIG_SYS_NIOS_CPU_MUL __nios_use_multiply__
CONFIG_SYS_NIOS_CPU_MSTEP __nios_use_mstep__
CONFIG_SYS_NIOS_CPU_STACK nasys_stack_top
CONFIG_SYS_NIOS_CPU_VEC_BASE nasys_vector_table
CONFIG_SYS_NIOS_CPU_VEC_SIZE nasys_vector_table_size
CONFIG_SYS_NIOS_CPU_VEC_NUMS
CONFIG_SYS_NIOS_CPU_RST_VECT nasys_reset_address
CONFIG_SYS_NIOS_CPU_DBG_CORE nasys_debug_core
CONFIG_SYS_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
CONFIG_SYS_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
CONFIG_SYS_NIOS_CPU_ROM_BASE na_boot_monitor_rom
CONFIG_SYS_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
CONFIG_SYS_NIOS_CPU_OCI_BASE nasys_oci_core
CONFIG_SYS_NIOS_CPU_OCI_SIZE
CONFIG_SYS_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
nasys_data_mem
CFG_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
CONFIG_SYS_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
nasys_data_mem_size
CFG_NIOS_CPU_SDRAM_BASE na_sdram
CFG_NIOS_CPU_SDRAM_SIZE na_sdram_size
CFG_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
CONFIG_SYS_NIOS_CPU_SDRAM_BASE na_sdram
CONFIG_SYS_NIOS_CPU_SDRAM_SIZE na_sdram_size
CONFIG_SYS_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
nasys_am29lv065d_flash_0
nasys_flash_0
CFG_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
CONFIG_SYS_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
T I M E R N I O S S D K [3]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_TIMER_NUMS nasys_timer_count
CFG_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
CFG_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
CFG_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
CONFIG_SYS_NIOS_CPU_TIMER_NUMS nasys_timer_count
CONFIG_SYS_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
[ptf]:period_units
[ptf]:mult
CFG_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
CFG_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
CFG_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
U A R T N I O S S D K [2]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_UART_NUMS nasys_uart_count
CFG_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
CFG_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
CFG_NIOS_CPU_UART[0-9]_BR [ptf]:baud
CFG_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
CFG_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
CFG_NIOS_CPU_UART[0-9]_PA [ptf]:parity
CFG_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
CFG_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
CONFIG_SYS_NIOS_CPU_UART_NUMS nasys_uart_count
CONFIG_SYS_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
CONFIG_SYS_NIOS_CPU_UART[0-9]_BR [ptf]:baud
CONFIG_SYS_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
CONFIG_SYS_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
CONFIG_SYS_NIOS_CPU_UART[0-9]_PA [ptf]:parity
CONFIG_SYS_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
P I O N I O S S D K [4]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_PIO_NUMS nasys_pio_count
CFG_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
CFG_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
CFG_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
CFG_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
CONFIG_SYS_NIOS_CPU_PIO_NUMS nasys_pio_count
CONFIG_SYS_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
[ptf]:has_out
[ptf]:has_in
CFG_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
CFG_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
CFG_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
S P I N I O S S D K [6]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_SPI_NUMS nasys_spi_count
CFG_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
CFG_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
CFG_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
CFG_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
CFG_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
CFG_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
CFG_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
CFG_NIOS_CPU_SPI[0-9]_* [ptf]:*
CONFIG_SYS_NIOS_CPU_SPI_NUMS nasys_spi_count
CONFIG_SYS_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
CONFIG_SYS_NIOS_CPU_SPI[0-9]_* [ptf]:*
I D E N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_IDE_NUMS nasys_usersocket_count
CFG_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
CONFIG_SYS_NIOS_CPU_IDE_NUMS nasys_usersocket_count
CONFIG_SYS_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
A S M I N I O S S D K [5]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_ASMI_NUMS nasys_asmi_count
CFG_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
CFG_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
CONFIG_SYS_NIOS_CPU_ASMI_NUMS nasys_asmi_count
CONFIG_SYS_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
E t h e r n e t ( L A N ) N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_LAN_NUMS
CFG_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
CFG_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
CFG_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
CFG_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
CFG_NIOS_CPU_LAN[0-9]_TYPE
CONFIG_SYS_NIOS_CPU_LAN_NUMS
CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE
s y s t e m c o m p o s i n g N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
CFG_NIOS_CPU_USER_TIMER (na_timer1)
CFG_NIOS_CPU_BUTTON_PIO (na_button_pio)
CFG_NIOS_CPU_LCD_PIO (na_lcd_pio)
CFG_NIOS_CPU_LED_PIO (na_led_pio)
CFG_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
CFG_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
CFG_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
CFG_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
CFG_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
CFG_NIOS_CPU_USER_SPI (na_spi)
CONFIG_SYS_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
CONFIG_SYS_NIOS_CPU_USER_TIMER (na_timer1)
CONFIG_SYS_NIOS_CPU_BUTTON_PIO (na_button_pio)
CONFIG_SYS_NIOS_CPU_LCD_PIO (na_lcd_pio)
CONFIG_SYS_NIOS_CPU_LED_PIO (na_led_pio)
CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
CONFIG_SYS_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
CONFIG_SYS_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
CONFIG_SYS_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
CONFIG_SYS_NIOS_CPU_USER_SPI (na_spi)
===============================================================================
......
api/api_storage.c
View file @ f61f1e15
......@@ -67,28 +67,28 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
void dev_stor_init(void)
{
#if defined(CONFIG_CMD_IDE)
specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
specs[ENUM_IDE].enum_started = 0;
specs[ENUM_IDE].enum_ended = 0;
specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
specs[ENUM_IDE].name = "ide";
#endif
#if defined(CONFIG_CMD_MMC)
specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE;
specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;
specs[ENUM_MMC].enum_started = 0;
specs[ENUM_MMC].enum_ended = 0;
specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
specs[ENUM_MMC].name = "mmc";
#endif
#if defined(CONFIG_CMD_SATA)
specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE;
specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
specs[ENUM_SATA].enum_started = 0;
specs[ENUM_SATA].enum_ended = 0;
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_CMD_SCSI)
specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
......
board/AtmarkTechno/suzaku/flash.c
View file @ f61f1e15
......@@ -24,7 +24,7 @@
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned long flash_init(void)
{
......
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
View file @ f61f1e15
......@@ -32,7 +32,7 @@
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
......@@ -45,10 +45,10 @@ phys_size_t initdram (int board_type)
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
#ifdef CFG_SDRAM_BASE0
| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
#ifdef CONFIG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
......@@ -57,17 +57,17 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
mbar_writeLong (MCFSDRAMC_DACR0,
mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE * 1024 * 1024;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CFG_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
#ifdef CONFIG_SYS_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
......@@ -76,25 +76,25 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE1 * 1024 * 1024;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
return size;
}
#if defined(CFG_DRAM_TEST)
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
......
board/BuS/EB+MCF-EV123/VCxK.c
View file @ f61f1e15
......@@ -25,7 +25,7 @@
#include <asm/m5282.h>
#include "VCxK.h"
vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
#define VCXK_BWS vcxk_bws
static ulong vcxk_driver;
......