Commit f71d9d91 authored by Matthew Fettke's avatar Matthew Fettke Committed by John Rigby
Browse files

ColdFire: Added MCF5275 cpu support.


Signed-off-by: default avatarMatthew Fettke <mfettke@videon-central.com>
Signed-off-by: default avatarTsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: default avatarJohn Rigby <jrigby@freescale.com>
parent 44e5b9ed
......@@ -431,6 +431,7 @@ D: Support for EP82xxM
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
D: Support for ColdFire MCF5275
N: Michal Simek
E: monstr@monstr.eu
......
......@@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
......@@ -47,6 +48,9 @@ endif
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
ifneq (,$(findstring CONFIG_M5275,$(is5275)))
PLATFORM_CPPFLAGS += -mcpu=5275
endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
......
......@@ -6,6 +6,9 @@
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
* MCF5275 additions
* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -180,6 +183,69 @@ int watchdog_init(void)
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
udelay(1000);
rcm->rcr = RCM_RCR_SOFTRST;
/* we don't return! */
return 0;
};
int checkcpu(void)
{
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
strmhz(buf, CFG_CLK));
return 0;
};
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdt->wsr = 0x5555;
wdt->wsr = 0xAAAA;
}
int watchdog_disable(void)
{
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdt->wsr = 0x5555; /* reset watchdog counter */
wdt->wsr = 0xAAAA;
wdt->wcr = 0; /* disable watchdog timer */
puts("WATCHDOG:disabled\n");
return (0);
}
int watchdog_init(void)
{
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdt->wcr = 0; /* disable watchdog */
/* set timeout and enable watchdog */
wdt->wmr =
((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
wdt->wsr = 0x5555; /* reset watchdog counter */
wdt->wsr = 0xAAAA;
puts("WATCHDOG:enabled\n");
return (0);
}
#endif /* #ifdef CONFIG_WATCHDOG */
#endif /* #ifdef CONFIG_M5275 */
#ifdef CONFIG_M5282
int checkcpu(void)
{
......
......@@ -10,6 +10,9 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* MCF5275 additions
* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -245,6 +248,114 @@ void uart_port_conf(void)
}
#endif /* #if defined(CONFIG_M5272) */
#if defined(CONFIG_M5275)
/*
* Breathe some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
/* Kill watchdog so we can initialize the PLL */
wdog_reg->wcr = 0;
/* Memory Controller: */
/* Flash */
csctrl_reg->ar0 = CFG_AR0_PRELIM;
csctrl_reg->cr0 = CFG_CR0_PRELIM;
csctrl_reg->mr0 = CFG_MR0_PRELIM;
#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
csctrl_reg->ar1 = CFG_AR1_PRELIM;
csctrl_reg->cr1 = CFG_CR1_PRELIM;
csctrl_reg->mr1 = CFG_MR1_PRELIM;
#endif
#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
csctrl_reg->ar2 = CFG_AR2_PRELIM;
csctrl_reg->cr2 = CFG_CR2_PRELIM;
csctrl_reg->mr2 = CFG_MR2_PRELIM;
#endif
#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
csctrl_reg->ar3 = CFG_AR3_PRELIM;
csctrl_reg->cr3 = CFG_CR3_PRELIM;
csctrl_reg->mr3 = CFG_MR3_PRELIM;
#endif
#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
csctrl_reg->ar4 = CFG_AR4_PRELIM;
csctrl_reg->cr4 = CFG_CR4_PRELIM;
csctrl_reg->mr4 = CFG_MR4_PRELIM;
#endif
#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
csctrl_reg->ar5 = CFG_AR5_PRELIM;
csctrl_reg->cr5 = CFG_CR5_PRELIM;
csctrl_reg->mr5 = CFG_MR5_PRELIM;
#endif
#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
csctrl_reg->ar6 = CFG_AR6_PRELIM;
csctrl_reg->cr6 = CFG_CR6_PRELIM;
csctrl_reg->mr6 = CFG_MR6_PRELIM;
#endif
#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
csctrl_reg->ar7 = CFG_AR7_PRELIM;
csctrl_reg->cr7 = CFG_CR7_PRELIM;
csctrl_reg->mr7 = CFG_MR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
gpio_reg->par_feci2c = 0x000F;
#endif
/* enable instruction cache now */
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
return (0);
}
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
gpio->par_uart |= UART0_ENABLE_MASK;
break;
case 1:
gpio->par_uart |= UART1_ENABLE_MASK;
break;
case 2:
gpio->par_uart |= UART2_ENABLE_MASK;
break;
}
}
#endif /* #if defined(CONFIG_M5275) */
#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
......
......@@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
......@@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
int interrupt_init(void)
......
......@@ -64,8 +64,18 @@ int get_clocks (void)
#endif /* CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5275)
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
/* Setup PLL */
pll->syncr = 0x01080000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK));
pll->syncr = 0x01000000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK));
#endif
gd->cpu_clk = CFG_CLK;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
......
......@@ -197,6 +197,17 @@ _copy_flash:
_after_flash_copy:
#endif
#ifdef CONFIG_M5275
/* Initialize IPSBAR */
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
#if 0
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
......@@ -394,6 +405,25 @@ icache_enable:
rts
#endif
#if defined(CONFIG_M5275)
/*
* Instruction cache only
*/
.globl icache_enable
icache_enable:
move.l #0x01400000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0x0000c000, %d0 /* Setup SDRAM caching */
movec %d0, %ACR0 /* Enable cache */
move.l #0x00000000, %d0 /* No other caching */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80400100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
moveq #1, %d0
move.l %d0, icache_state
rts
#endif
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
......
......@@ -180,6 +180,30 @@
#endif
#endif /* CONFIG_M5272 */
#ifdef CONFIG_M5275
#include <asm/immap_5275.h>
#include <asm/m5275.h>
#define CFG_FEC0_IOBASE (MMAP_FEC0)
#define CFG_FEC1_IOBASE (MMAP_FEC1)
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (192)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR3)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5275 */
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
......
/*
* MCF5274/5 Internal Memory Map
*
* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
* Based on work Copyright (c) 2003 Josef Baumgartner
* <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5275__
#define __IMMAP_5275__
#define MMAP_SCM (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
#define MMAP_FBCS (CFG_MBAR + 0x00000080)
#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
#define MMAP_UART0 (CFG_MBAR + 0x00000200)
#define MMAP_UART1 (CFG_MBAR + 0x00000240)
#define MMAP_UART2 (CFG_MBAR + 0x00000280)
#define MMAP_I2C (CFG_MBAR + 0x00000300)
#define MMAP_QSPI (CFG_MBAR + 0x00000340)
#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
#define MMAP_GPIO (CFG_MBAR + 0x00100000)
#define MMAP_RCM (CFG_MBAR + 0x00110000)
#define MMAP_CCM (CFG_MBAR + 0x00110004)
#define MMAP_PLL (CFG_MBAR + 0x00120000)
#define MMAP_EPORT (CFG_MBAR + 0x00130000)
#define MMAP_WDOG (CFG_MBAR + 0x00140000)
#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
#define MMAP_MDHA (CFG_MBAR + 0x00190000)
#define MMAP_RNG (CFG_MBAR + 0x001A0000)
#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
#define MMAP_USB (CFG_MBAR + 0x001C0000)
#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
/* System configuration registers
*/
typedef struct sys_ctrl {
u32 ipsbar;
u32 res1;
u32 rambar;
u32 res2;
u8 crsr;
u8 cwcr;
u8 lpicr;
u8 cwsr;
u8 res3[8];
u32 mpark;
u8 mpr;
u8 res4[3];
u8 pacr0;
u8 pacr1;
u8 pacr2;
u8 pacr3;
u8 pacr4;
u8 res5;
u8 pacr5;
u8 pacr6;
u8 pacr7;
u8 res6;
u8 pacr8;
u8 res7;
u8 gpacr;
u8 res8[3];
} sysctrl_t;
/* SDRAM controller registers, offset: 0x040
*/
typedef struct sdram_ctrl {
u32 sdmr;
u32 sdcr;
u32 sdcfg1;
u32 sdcfg2;
u32 sdbar0;
u32 sdbmr0;
u32 sdbar1;
u32 sdbmr1;
} sdramctrl_t;
/* Chip select module registers, offset: 0x080
*/
typedef struct cs_ctlr {
u16 ar0;
u16 res1;
u32 mr0;
u16 res2;
u16 cr0;
u16 ar1;
u16 res3;
u32 mr1;
u16 res4;
u16 cr1;
u16 ar2;
u16 res5;
u32 mr2;
u16 res6;
u16 cr2;
u16 ar3;
u16 res7;
u32 mr3;
u16 res8;
u16 cr3;
u16 ar4;
u16 res9;
u32 mr4;
u16 res10;
u16 cr4;
u16 ar5;
u16 res11;
u32 mr5;
u16 res12;
u16 cr5;
u16 ar6;
u16 res13;
u32 mr6;
u16 res14;
u16 cr6;
u16 ar7;
u16 res15;
u32 mr7;
u16 res16;
u16 cr7;
} csctrl_t;
/* DMA module registers, offset 0x100
*/
typedef struct dma_ctrl {
u32 sar;
u32 dar;
u32 dsrbcr;
u32 dcr;
} dma_t;
/* QSPI module registers, offset 0x340
*/
typedef struct qspi_ctrl {
u16 qmr;
u8 res1[2];
u16 qdlyr;
u8 res2[2];
u16 qwr;
u8 res3[2];
u16 qir;
u8 res4[2];
u16 qar;
u8 res5[2];
u16 qdr;
u8 res6[2];
} qspi_t;
/* Interrupt module registers, offset 0xc00
*/
typedef struct int_ctrl {
u32 iprh0;
u32 iprl0;
u32 imrh0;
u32 imrl0;
u32 frch0;
u32 frcl0;
u8 irlr;
u8 iacklpr;
u8 res1[0x26];
u8 icr0[64]; /* No ICR0, done this way for readability */
u8 res2[0x60];
u8 swiack0;
u8 res3[3];
u8 Lniack0_1;
u8 res4[3];
u8 Lniack0_2;
u8 res5[3];
u8 Lniack0_3;
u8 res6[3];
u8 Lniack0_4;
u8 res7[3];
u8 Lniack0_5;
u8 res8[3];
u8 Lniack0_6;
u8 res9[3];
u8 Lniack0_7;
u8 res10[3];
} int0_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
/* Port Output Data Registers */
u8 podr_res1[4];
u8 podr_busctl;
u8 podr_addr;
u8 podr_res2[2];
u8 podr_cs;
u8 podr_res3;
u8 podr_fec0h;
u8 podr_fec0l;
u8 podr_feci2c;
u8 podr_qspi;
u8 podr_sdram;
u8 podr_timerh;
u8 podr_timerl;
u8 podr_uartl;
u8 podr_fec1h;
u8 podr_fec1l;
u8 podr_bs;
u8 podr_res4;
u8 podr_usbh;
u8 podr_usbl;
u8 podr_uarth;
u8 podr_res5[3];
/* Port Data Direction Registers */
u8 pddr_res1[4];
u8 pddr_busctl;
u8 pddr_addr;
u8 pddr_res2[2];
u8 pddr_cs;
u8 pddr_res3;
u8 pddr_fec0h;
u8 pddr_fec0l;
u8 pddr_feci2c;
u8 pddr_qspi;
u8 pddr_sdram;
u8 pddr_timerh;
u8 pddr_timerl;
u8 pddr_uartl;
u8 pddr_fec1h;
u8 pddr_fec1l;
u8 pddr_bs;
u8 pddr_res4;
u8 pddr_usbh;
u8 pddr_usbl;
u8 pddr_uarth;
u8 pddr_res5[3];
/* Port Pin Data/Set Registers */
u8 ppdsdr_res1[4];
u8 ppdsdr_busctl;
u8 ppdsdr_addr;
u8 ppdsdr_res2[2];
u8 ppdsdr_cs;
u8 ppdsdr_res3;
u8 ppdsdr_fec0h;
u8 ppdsdr_fec0l;
u8 ppdsdr_feci2c;
u8 ppdsdr_qspi;
u8 ppdsdr_sdram;
u8 ppdsdr_timerh;
u8 ppdsdr_timerl;
u8 ppdsdr_uartl;
u8 ppdsdr_fec1h;
u8 ppdsdr_fec1l;
u8 ppdsdr_bs;
u8 ppdsdr_res4;
u8 ppdsdr_usbh;
u8 ppdsdr_usbl;
u8 ppdsdr_uarth;