Commit f7e78f3b authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nobuhiro Iwamatsu

sh: use write{8,16,32} in all lowlevel_init

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent e4430779
......@@ -22,6 +22,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/macro.h>
.global lowlevel_init
......@@ -33,59 +34,35 @@ lowlevel_init:
/*
* Set frequency multipliers and dividers in FRQCR.
*/
mov.l WTCSR_A, r1
mov.l WTCSR_D, r0
mov.w r0, @r1
write16 WTCSR_A, WTCSR_D
mov.l WTCNT_A, r1
mov.l WTCNT_D, r0
mov.w r0, @r1
write16 WTCNT_A, WTCNT_D
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.w r0, @r1
write16 FRQCR_A, FRQCR_D
/*
* Setup CS0 (Flash).
*/
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
write32 CS0WCR_A, CS0WCR_D
/*
* Setup CS3 (SDRAM).
*/
mov.l CS3BCR_A, r1
mov.l CS3BCR_D, r0
mov.l r0, @r1
write32 CS3BCR_A, CS3BCR_D
mov.l CS3WCR_A, r1
mov.l CS3WCR_D, r0
mov.l r0, @r1
write32 CS3WCR_A, CS3WCR_D
mov.l SDCR_A, r1
mov.l SDCR_D1, r0
mov.l r0, @r1
write32 SDCR_A, SDCR_D1
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.l r0, @r1
write32 RTCSR_A, RTCSR_D
mov.l RTCNT_A, r1
mov.l RTCNT_D, r0
mov.l r0, @r1
write32 RTCNT_A, RTCNT_D
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.l r0, @r1
write32 RTCOR_A, RTCOR_D
mov.l SDCR_A, r1
mov.l SDCR_D2, r0
mov.l r0, @r1
write32 SDCR_A, SDCR_D2
mov.l SDMR3_A, r1
mov.l SDMR3_D, r0
......
......@@ -27,6 +27,7 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
......@@ -43,165 +44,94 @@
lowlevel_init:
/* Address of Cache Control Register */
mov.l CCR_A, r1
/*Instruction Cache Invalidate */
mov.l CCR_D, r0
mov.l r0, @r1
/*
* Cache Control Register
* Instruction Cache Invalidate
*/
write32 CCR_A, CCR_D
/* Address of MMU Control Register */
mov.l MMUCR_A, r1
/* TI == TLB Invalidate bit */
mov.l MMUCR_D, r0
mov.l r0, @r1
/*
* Address of MMU Control Register
* TI == TLB Invalidate bit
*/
write32 MMUCR_A, MMUCR_D
/* Address of Power Control Register 0 */
mov.l MSTPCR0_A, r1
mov.l MSTPCR0_D, r0
mov.l r0, @r1
write32 MSTPCR0_A, MSTPCR0_D
/* Address of Power Control Register 2 */
mov.l MSTPCR2_A, r1
mov.l MSTPCR2_D, r0
mov.l r0, @r1
write32 MSTPCR2_A, MSTPCR2_D
mov.l SBSCR_A, r1
mov.w SBSCR_D, r0
mov.w r0, @r1
write16 SBSCR_A, SBSCR_D
mov.l PSCR_A, r1
mov.w PSCR_D, r0
mov.w r0, @r1
write16 PSCR_A, PSCR_D
/* 0xA4520004 (Watchdog Control / Status Register) */
! mov.l RWTCSR_A, r1
/* 0xA507 -> timer_STOP/WDT_CLK=max */
! mov.w RWTCSR_D_1, r0
! mov.w r0, @r1
! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
/* 0xA4520000 (Watchdog Count Register) */
mov.l RWTCNT_A, r1
/*0x5A00 -> Clear */
mov.w RWTCNT_D, r0
mov.w r0, @r1
write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
/* 0xA4520004 (Watchdog Control / Status Register) */
mov.l RWTCSR_A, r1
/* 0xA504 -> timer_STOP/CLK=500ms */
mov.w RWTCSR_D_2, r0
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
/* 0xA4150000 Frequency control register */
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0 !
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D
mov.l CCR_A, r1
mov.l CCR_D_2, r0
mov.l r0, @r1
write32 CCR_A, CCR_D_2
bsc_init:
mov.l PSELA_A, r1
mov.w PSELA_D, r0
mov.w r0, @r1
write16 PSELA_A, PSELA_D
mov.l DRVCR_A, r1
mov.w DRVCR_D, r0
mov.w r0, @r1
write16 DRVCR_A, DRVCR_D
mov.l PCCR_A, r1
mov.w PCCR_D, r0
mov.w r0, @r1
write16 PCCR_A, PCCR_D
mov.l PECR_A, r1
mov.w PECR_D, r0
mov.w r0, @r1
write16 PECR_A, PECR_D
mov.l PJCR_A, r1
mov.w PJCR_D, r0
mov.w r0, @r1
write16 PJCR_A, PJCR_D
mov.l PXCR_A, r1
mov.w PXCR_D, r0
mov.w r0, @r1
write16 PXCR_A, PXCR_D
mov.l CMNCR_A, r1 ! CMNCR address -> R1
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l r0, @r1 ! CMNCR set
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
mov.l r0, @r1 ! CS0BCR set
write32 CS0BCR_A, CS0BCR_D
mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
mov.l r0, @r1 ! CS2BCR set
write32 CS2BCR_A, CS2BCR_D
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
mov.l r0, @r1 ! CS4BCR set
write32 CS4BCR_A, CS4BCR_D
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
mov.l r0, @r1 ! CS5ABCR set
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
mov.l r0, @r1 ! CS5BBCR set
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
mov.l r0, @r1 ! CS6ABCR set
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
mov.l r0, @r1 ! CS0WCR set
write32 CS0WCR_A, CS0WCR_D
mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
mov.l r0, @r1 ! CS2WCR set
write32 CS2WCR_A, CS2WCR_D
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
mov.l r0, @r1 ! CS4WCR set
write32 CS4WCR_A, CS4WCR_D
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
mov.l r0, @r1 ! CS5AWCR set
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
mov.l r0, @r1 ! CS5BWCR set
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
mov.l r0, @r1 ! CS6AWCR set
write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
mov.l SDCR_A, r1 ! SB_SDCR address -> R1
mov.l SDCR_D, r0 ! SB_SDCR data -> R0
mov.l r0, @r1 ! SB_SDCR set
write32 SDCR_A, SDCR_D
mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
mov.l r0, @r1 ! SB_SDWCR set
write32 SDWCR_A, SDWCR_D
mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
mov.l r0, @r1 ! SB_SDPCR set
write32 SDPCR_A, SDPCR_D
mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
mov.l r0, @r1 ! SB_RTCOR set
write32 RTCOR_A, RTCOR_D
mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
mov.l r0, @r1 ! SB_RTCSR set
write32 RTCSR_A, RTCSR_D
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
write8 SDMR3_A, #0x00
! BL bit off (init = ON) (?!?)
......
......@@ -29,6 +29,7 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
......@@ -65,61 +66,37 @@
lowlevel_init:
mov.l CCR_A, r1 ! CCR Address
mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1
write32 CCR_A, CCR_D_DISABLE
init_bsc:
mov.l FRQCR_A, r1 /* FRQCR Address */
mov.l FRQCR_D, r0 /* FRQCR Data */
mov.w r0, @r1
write16 FRQCR_A, FRQCR_D
mov.l BCR1_A, r1 /* BCR1 Address */
mov.l BCR1_D, r0 /* BCR1 Data */
mov.l r0, @r1
write32 BCR1_A, BCR1_D
mov.l BCR2_A, r1 /* BCR2 Address */
mov.l BCR2_D, r0 /* BCR2 Data */
mov.w r0, @r1
write16 BCR2_A, BCR2_D
mov.l WCR1_A, r1 /* WCR1 Address */
mov.l WCR1_D, r0 /* WCR1 Data */
mov.l r0, @r1
write32 WCR1_A, WCR1_D
mov.l WCR2_A, r1 /* WCR2 Address */
mov.l WCR2_D, r0 /* WCR2 Data */
mov.l r0, @r1
write32 WCR2_A, WCR2_D
mov.l WCR3_A, r1 /* WCR3 Address */
mov.l WCR3_D, r0 /* WCR3 Data */
mov.l r0, @r1
write32 WCR3_A, WCR3_D
mov.l MCR_A, r1 /* MCR Address */
mov.l MCR_D1, r0 /* MCR Data1 */
mov.l r0, @r1
write32 MCR_A, MCR_D1
mov.l SDMR3_A, r1 /* Set SDRAM mode */
mov #0, r0
mov.b r0, @r1
/* Set SDRAM mode */
write8 SDMR3_A, #0
! Do you need PCMCIA setting?
! If so, please add the lines here...
mov.l RTCNT_A, r1 /* RTCNT Address */
mov.l RTCNT_D, r0 /* RTCNT Data */
mov.w r0, @r1
write16 RTCNT_A, RTCNT_D
mov.l RTCOR_A, r1 /* RTCOR Address */
mov.l RTCOR_D, r0 /* RTCOR Data */
mov.w r0, @r1
write16 RTCOR_A, RTCOR_D
mov.l RTCSR_A, r1 /* RTCSR Address */
mov.l RTCSR_D, r0 /* RTCSR Data */
mov.w r0, @r1
write16 RTCSR_A, RTCSR_D
write16 RFCR_A, RFCR_D
mov.l RFCR_A, r1 /* RFCR Address */
mov.l RFCR_D, r0 /* RFCR Data */
mov.w r0, @r1 /* Clear reflesh counter */
/* Wait DRAM refresh 30 times */
mov #30, r3
1:
......@@ -128,13 +105,10 @@ init_bsc:
cmp/hi r3, r2
bf 1b
mov.l MCR_A, r1 /* MCR Address */
mov.l MCR_D2, r0 /* MCR Data2 */
mov.l r0, @r1
write32 MCR_A, MCR_D2
mov.l SDMR3_A, r1 /* Set SDRAM mode */
mov #0, r0
mov.b r0, @r1
/* Set SDRAM mode */
write8 SDMR3_A, #0
rts
nop
......
......@@ -27,6 +27,7 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
......@@ -42,139 +43,81 @@
.align 2
lowlevel_init:
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D, r0 ! Instruction Cache Invalidate
mov.l r0, @r1
write32 CCR_A, CCR_D ! Address of Cache Control Register
! Instruction Cache Invalidate
mov.l MMUCR_A, r1 ! Address of MMU Control Register
mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
mov.l r0, @r1
write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
! TI == TLB Invalidate bit
mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
mov.l MSTPCR0_D, r0 !
mov.l r0, @r1
write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
mov.l MSTPCR2_D, r0 !
mov.l r0, @r1
write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
mov.l PFC_PULCR_A, r1
mov.w PFC_PULCR_D, r0
mov.w r0,@r1
write16 PFC_PULCR_A, PFC_PULCR_D
mov.l PFC_DRVCR_A, r1
mov.w PFC_DRVCR_D, r0
mov.w r0, @r1
write16 PFC_DRVCR_A, PFC_DRVCR_D
mov.l SBSCR_A, r1 !
mov.w SBSCR_D, r0 !
mov.w r0, @r1
write16 SBSCR_A, SBSCR_D
mov.l PSCR_A, r1 !
mov.w PSCR_D, r0 !
mov.w r0, @r1
write16 PSCR_A, PSCR_D
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
! 0xA507 -> timer_STOP / WDT_CLK = max
mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
mov.w r0, @r1
write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
! 0x5A00 -> Clear
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
! 0xA504 -> timer_STOP / CLK = 500ms
mov.l DLLFRQ_A, r1 ! 20080115
mov.l DLLFRQ_D, r0 ! 20080115
mov.l r0, @r1
write32 DLLFRQ_A, DLLFRQ_D ! 20080115
! 20080115
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
mov.l FRQCR_D, r0 ! 20080115
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
! 20080115
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D_2, r0 ! ??
mov.l r0, @r1
write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
! ??
bsc_init:
mov.l CMNCR_A, r1 ! CMNCR address -> R1
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l r0, @r1 ! CMNCR set
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
mov.l r0, @r1 ! CS0BCR set
write32 CS0BCR_A, CS0BCR_D
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
mov.l r0, @r1 ! CS4BCR set
write32 CS4BCR_A, CS4BCR_D
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
mov.l r0, @r1 ! CS5ABCR set
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
mov.l r0, @r1 ! CS5BBCR set
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
mov.l r0, @r1 ! CS6ABCR set
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
mov.l r0, @r1 ! CS0WCR set
write32 CS0WCR_A, CS0WCR_D
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
mov.l r0, @r1 ! CS4WCR set
write32 CS4WCR_A, CS4WCR_D
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
mov.l r0, @r1 ! CS5AWCR set
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
mov.l r0, @r1 ! CS5BWCR set
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
mov.l r0, @r1 ! CS6AWCR set
write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
mov.l SDCR_A, r1 ! SB_SDCR address -> R1
mov.l SDCR_D, r0 ! SB_SDCR data -> R0
mov.l r0, @r1 ! SB_SDCR set
write32 SDCR_A, SDCR_D
mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
mov.l r0, @r1 ! SB_SDWCR set
write32 SDWCR_A, SDWCR_D
mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
mov.l r0, @r1 ! SB_SDPCR set
write32 SDPCR_A, SDPCR_D
mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
mov.l r0, @r1 ! SB_RTCOR set
write32 RTCOR_A, RTCOR_D
mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
mov.l r0, @r1
write32 RTCNT_A, RTCNT_D
mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
mov.l r0, @r1 ! SB_RTCSR set
write32 RTCSR_A, RTCSR_D
mov.l RFCR_A, r1 ! SB_RFCR address -> R1
mov.l RFCR_D, r0 ! SB_RFCR data -> R0
mov.l r0, @r1
write32 RFCR_A, RFCR_D
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
write8 SDMR3_A, #0x00
! BL bit off (init = ON) (?!?)
......
......@@ -23,6 +23,7 @@
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
......@@ -38,113 +39,59 @@
.align 2
lowlevel_init:
mov.l DRVCRA_A, r1
mov.l DRVCRA_D, r0
mov.w r0, @r1
write16 DRVCRA_A, DRVCRA_D
mov.l DRVCRB_A, r1
mov.l DRVCRB_D, r0
mov.w r0, @r1
write16 DRVCRB_A, DRVCRB_D
mov.l RWTCSR_A, r1
mov.l RWTCSR_D1, r0
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D1
mov.l RWTCNT_A, r1
mov.l RWTCNT_D, r0
mov.w r0, @r1
write16 RWTCNT_A, RWTCNT_D
mov.l RWTCSR_A, r1
mov.l RWTCSR_D2, r0
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D2
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
write32 CS4BCR_A, CS4BCR_D
mov.l CS5ABCR_A, r1
mov.l CS5ABCR_D, r0
mov.l r0, @r1
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS5BBCR_A, r1
mov.l CS5BBCR_D, r0
mov.l r0, @r1
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6ABCR_A, r1
mov.l CS6ABCR_D, r0
mov.l r0, @r1
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS6BBCR_A, r1
mov.l CS6BBCR_D, r0
mov.l r0, @r1
write32 CS6BBCR_A, CS6BBCR_D
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
write32 CS0WCR_A, CS0WCR_D
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
write32 CS4WCR_A, CS4WCR_D
mov.l CS5AWCR_A, r1
mov.l CS5AWCR_D, r0
mov.l r0, @r1
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS5BWCR_A, r1
mov.l CS5BWCR_D, r0
mov.l r0, @r1
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6AWCR_A, r1
mov.l CS6AWCR_D, r0
mov.l r0, @r1
write32 CS6AWCR_A, CS6AWCR_D
mov.l CS6BWCR_A, r1
mov.l CS6BWCR_D, r0
mov.l r0, @r1
write32 CS6BWCR_A, CS6BWCR_D
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D1, r0
mov.l r0, @r1
write32 SBSC_SDCR_A, SBSC_SDCR_D1
mov.l SBSC_SDWCR_A, r1
mov.l SBSC_SDWCR_D, r0
mov.l r0, @r1
write32 SBSC_SDWCR_A, SBSC_SDWCR_D
mov.l SBSC_SDPCR_A, r1
mov.l SBSC_SDPCR_D, r0