Commit f7fa2f37 authored by Bo Shen's avatar Bo Shen Committed by Albert ARIBAUD
Browse files

arm : Atmel : add at91sam9x5ek board support



Add at91sam9x5ek board support, this board support the following SoCs
  AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: default avatarBo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: default avatarAndreas Bießmann <andreas.devel@googlemail.com>
parent 963333e9
......@@ -875,6 +875,9 @@ Michael Schwingen <michael@schwingen.org>
actux4 xscale/ixp
dvlhost xscale/ixp
Bo Shen <voice.shen@atmel.com>
at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
......
......@@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
COBJS-$(CONFIG_AT91_EFLASH) += eflash.o
COBJS-$(CONFIG_AT91_LED) += led.o
COBJS-y += clock.o
......
/*
* Copyright (C) 2012 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
unsigned int get_chip_id(void)
{
/* The 0x40 is the offset of cidr in DBGU */
return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
}
unsigned int get_extension_chip_id(void)
{
/* The 0x44 is the offset of exid in DBGU */
return readl(ATMEL_BASE_DBGU + 0x44);
}
unsigned int has_emac1()
{
return cpu_is_at91sam9x25();
}
unsigned int has_emac0()
{
return !(cpu_is_at91sam9g15());
}
unsigned int has_lcdc()
{
return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35();
}
char *get_cpu_name()
{
unsigned int extension_id = get_extension_chip_id();
if (cpu_is_at91sam9x5()) {
switch (extension_id) {
case ARCH_EXID_AT91SAM9G15:
return CONFIG_SYS_AT91_G15_CPU_NAME;
case ARCH_EXID_AT91SAM9G25:
return CONFIG_SYS_AT91_G25_CPU_NAME;
case ARCH_EXID_AT91SAM9G35:
return CONFIG_SYS_AT91_G35_CPU_NAME;
case ARCH_EXID_AT91SAM9X25:
return CONFIG_SYS_AT91_X25_CPU_NAME;
case ARCH_EXID_AT91SAM9X35:
return CONFIG_SYS_AT91_X35_CPU_NAME;
default:
return CONFIG_SYS_AT91_UNKNOWN_CPU;
}
} else {
return CONFIG_SYS_AT91_UNKNOWN_CPU;
}
}
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0))
at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
if (cs_mask & (1 << 1))
at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
if (cs_mask & (1 << 2))
at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
if (cs_mask & (1 << 3))
at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
if (cs_mask & (1 << 5))
at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
if (cs_mask & (1 << 6))
at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
if (cs_mask & (1 << 7))
at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE;
at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0))
at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 1))
at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
if (cs_mask & (1 << 2))
at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
if (cs_mask & (1 << 3))
at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 5))
at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
if (cs_mask & (1 << 6))
at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
if (cs_mask & (1 << 7))
at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
}
#endif
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
if (has_emac0()) {
/* Enable EMAC0 clock */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
/* EMAC0 pins setup */
at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
}
if (has_emac1()) {
/* Enable EMAC1 clock */
writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
/* EMAC1 pins setup */
at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
}
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}
#endif
......@@ -154,7 +154,8 @@ int at91_clock_init(unsigned long main_clock)
* For now, assume this parentage won't change.
*/
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
|| defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
......@@ -168,7 +169,14 @@ int at91_clock_init(unsigned long main_clock)
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
|| defined(CONFIG_AT91SAM9X5)
/* mdiv <==> divisor
* 0 <==> 1
* 1 <==> 2
* 2 <==> 4
* 3 <==> 3
*/
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
......
......@@ -23,6 +23,8 @@
#include <asm/arch/at91cap9_matrix.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#include <asm/arch/at91sam9g45_matrix.h>
#elif defined(CONFIG_AT91SAM9X5)
#include <asm/arch/at91sam9x5_matrix.h>
#else
#error "Unsupported AT91SAM9/CAP9 processor"
#endif
......
/*
* Chip-specific header file for the AT91SAM9x5 family
*
* Copyright (C) 2012 Atmel Corporation.
*
* Definitions for the SoC:
* AT91SAM9x5
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __AT91SAM9X5_H__
#define __AT91SAM9X5_H__
/*
* Peripheral identifiers/interrupts.
*/
#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD) */
#define ATMEL_ID_USART0 5 /* USART 0 */
#define ATMEL_ID_USART1 6 /* USART 1 */
#define ATMEL_ID_USART2 7 /* USART 2 */
#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */
#define ATMEL_ID_UART0 15 /* UART 0 */
#define ATMEL_ID_UART1 16 /* UART 1 */
#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
#define ATMEL_ID_ADC 19 /* ADC Controller */
#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */
#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */
#define ATMEL_ID_LCDC 25 /* LCD Controller */
#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
/*
* User Peripheral physical base addresses.
*/
#define ATMEL_BASE_SPI0 0xf0000000
#define ATMEL_BASE_SPI1 0xf0004000
#define ATMEL_BASE_HSMCI0 0xf0008000
#define ATMEL_BASE_HSMCI1 0xf000c000
#define ATMEL_BASE_SSC 0xf0010000
#define ATMEL_BASE_CAN0 0xf8000000
#define ATMEL_BASE_CAN1 0xf8004000
#define ATMEL_BASE_TC0 0xf8008000
#define ATMEL_BASE_TC1 0xf8008040
#define ATMEL_BASE_TC2 0xf8008080
#define ATMEL_BASE_TC3 0xf800c000
#define ATMEL_BASE_TC4 0xf800c040
#define ATMEL_BASE_TC5 0xf800c080
#define ATMEL_BASE_TWI0 0xf8010000
#define ATMEL_BASE_TWI1 0xf8014000
#define ATMEL_BASE_TWI2 0xf8018000
#define ATMEL_BASE_USART0 0xf801c000
#define ATMEL_BASE_USART1 0xf8020000
#define ATMEL_BASE_USART2 0xf8024000
#define ATMEL_BASE_USART3 0xf8028000
#define ATMEL_BASE_EMAC0 0xf802c000
#define ATMEL_BASE_EMAC1 0xf8030000
#define ATMEL_BASE_PWM 0xf8034000
#define ATMEL_BASE_LCDC 0xf8038000
#define ATMEL_BASE_UDPHS 0xf803c000
#define ATMEL_BASE_UART0 0xf8040000
#define ATMEL_BASE_UART1 0xf8044000
#define ATMEL_BASE_ISI 0xf8048000
#define ATMEL_BASE_ADC 0xf804c000
#define ATMEL_BASE_SYS 0xffffc000
/*
* System Peripherals
*/
#define ATMEL_BASE_MATRIX 0xffffde00
#define ATMEL_BASE_PMECC 0xffffe000
#define ATMEL_BASE_PMERRLOC 0xffffe600
#define ATMEL_BASE_DDRSDRC 0xffffe800
#define ATMEL_BASE_SMC 0xffffea00
#define ATMEL_BASE_DMAC0 0xffffec00
#define ATMEL_BASE_DMAC1 0xffffee00
#define ATMEL_BASE_AIC 0xfffff000
#define ATMEL_BASE_DBGU 0xfffff200
#define ATMEL_BASE_PIOA 0xfffff400
#define ATMEL_BASE_PIOB 0xfffff600
#define ATMEL_BASE_PIOC 0xfffff800
#define ATMEL_BASE_PIOD 0xfffffa00
#define ATMEL_BASE_PMC 0xfffffc00
#define ATMEL_BASE_RSTC 0xfffffe00
#define ATMEL_BASE_SHDWC 0xfffffe10
#define ATMEL_BASE_PIT 0xfffffe30
#define ATMEL_BASE_WDT 0xfffffe40
#define ATMEL_BASE_GPBR 0xfffffe60
#define ATMEL_BASE_RTC 0xfffffeb0
/*
* Internal Memory.
*/
#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
/* 9x5 series chip id definitions */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_VERSION_MASK 0x1f
#define ARCH_EXID_AT91SAM9G15 0x00000000
#define ARCH_EXID_AT91SAM9G35 0x00000001
#define ARCH_EXID_AT91SAM9X35 0x00000002
#define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004
#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5)
#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
(get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
(get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
(get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
(get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
(get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
/*
* Cpu Name
*/
#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15"
#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25"
#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35"
#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25"
#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35"
#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type"
#define ATMEL_CPU_NAME get_cpu_name()
/*
* Other misc defines
*/
#define ATMEL_PIO_PORTS 4
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
/*
* at91sam9x5 specific prototypes
*/
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);
unsigned int get_extension_chip_id(void);
unsigned int has_emac1(void);
unsigned int has_emac0(void);
unsigned int has_lcdc(void);
char *get_cpu_name(void);
#endif
#endif
/*
* Matrix-centric header file for the AT91SAM9X5 family
*
* Copyright (C) 2012 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9X5 preliminary datasheet.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __AT91SAM9X5_MATRIX_H__
#define __AT91SAM9X5_MATRIX_H__
#ifndef __ASSEMBLY__
struct at91_matrix {
u32 mcfg[16];
u32 scfg[16];
u32 pras[16][2];
u32 mrcr; /* 0x100 Master Remap Control */
u32 filler[7];
u32 ebicsa;
u32 filler4[47];
u32 wpmr;
u32 wpsr;
};
#endif /* __ASSEMBLY__ */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0)
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
#define AT91_MATRIX_M0PR_SHIFT 0
#define AT91_MATRIX_M1PR_SHIFT 4
#define AT91_MATRIX_M2PR_SHIFT 8
#define AT91_MATRIX_M3PR_SHIFT 12
#define AT91_MATRIX_M4PR_SHIFT 16
#define AT91_MATRIX_M5PR_SHIFT 20
#define AT91_MATRIX_M6PR_SHIFT 24
#define AT91_MATRIX_M7PR_SHIFT 28
#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
#define AT91_MATRIX_RCB0 (1 << 0)
#define AT91_MATRIX_RCB1 (1 << 1)
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
#define AT91_MATRIX_MP_OFF (0 << 25)
#define AT91_MATRIX_MP_ON (1 << 25)
#endif
......@@ -37,6 +37,8 @@
# include <asm/arch/at91sam9rl.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
#elif defined(CONFIG_AT91CAP9)
# include <asm/arch/at91cap9.h>
#elif defined(CONFIG_AT91X40)
......
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian@popies.net>
# Lead Tech Design <www.leadtechdesign.com>
#
# (C) Copyright 2012
# Bo Shen <voice.shen@atmel.com>
# Atmel corporation <www.atmel.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += at91sam9x5ek.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk