Commit f9e4d046 authored by Padmavathi Venna's avatar Padmavathi Venna Committed by Minkyu Kang
Browse files

Exynos: clock: Correct pwm source clk selection



MPLL is selected as the source clk of pwm by default

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.
Signed-off-by: default avatarPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
parent 12a46a38
......@@ -343,7 +343,7 @@
#define TOP2_VAL 0x0110000
/* CLK_SRC_PERIC0 */
#define PWM_SEL 0
#define PWM_SEL 6
#define UART3_SEL 6
#define UART2_SEL 6
#define UART1_SEL 6
......
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